Re: [buildcheapeeg]new input stage, eagle files

From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2001-05-20 15:55:17


Hi,

----- Original Message -----
From: <jiva_at_humboldt1.com>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Saturday, May 19, 2001 8:47 PM
Subject: Re: [buildcheapeeg]new input stage, eagle files

> >
> > The schematic of the analog part should be complete so far. However
> I have not
> > done a complete simulation yet to verify all functions. A few parts
> values
> > have to be calculated yet.
> > If anyone has comments or improvements please let me know.
> >
>
>
> I don't mean to add more work but might it be possible to add
> a companion text file that explains the function of various
> "blocks" in the design?

1) C1,R1 forms an input side differential mode HP with fc=0.16Hz to
prevent IC1 from saturation by electrode offset DC-voltages.
2) C2,R2 forms an impedance symmetry compensation network.
3) An additional purpose of of R1,C1,C2,R2 is to protect the user from
worst case circuit failures of IC1 (power lines shorted internally to input lines)
4) IC2A is a shield driver that reduces the effective (shielded) electrode
cable capacity by the open loop gain of IC2A
5) IC2B is part of a servo circuit, that reduces common mode voltages at the
amplifier inputs (IC1) by amplifying (only) the common mode voltage, inverting it
and feeding it back into the users right leg. (right leg driver circuit). By this
The common mode suppression of IC1 is extended.
6) C35,R41 is a HP (fc=0.16Hz) that suppresses the amplified offset voltge of the INA114
(max 50uV RTI * 1000)
7)P2 adjusts the overall gain to 7812.5 so that the full scale input range of 512uVpp is scaled
to the 0..4V input range of the AT90S4433 ADC-part.
8)IC3A, IC3B forms a 5-pole Sallen Key Butterworth Lop Pass with 75Hz cutoff frequency.
(5th pole is on the digital board)
9) IC8A buffers the uref/2 voltage

>
> I noticed Porr's design has user adjustable gain in the preamp.
> Might that be desirable?

I assume, that there is not much space left on the RS232analog03-board.
With a future 16bit ADC-board, adjustable gain could be obsolete.
For an exact calculation it would be desirable to know, what input
voltage-ranges should be processed.
The new rs232eeg03analog has an input range of 512uVpp
and a resolution of 0.5uV.

Regards,

Joerg



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