From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2001-12-31 14:08:51
Hi Andreas ,
----- Original Message -----
From: Andreas Robinson <sleeper75se_at_yahoo.se>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Saturday, December 29, 2001 10:28 PM
Subject: [buildcheapeeg] Re: Input protection
...
> Perhaps the best place to connect all emitters to
> would be the output of the reference input amplifier
> (AMP0 in fig3, artikel7) Then the emitter and
> collector would see the same potential and it would
> always be very close (< 0.1V) to what the base sees,
> under normal circumstances.
This could be a solution. However you lose the enhancement
of the protection circuit impedance by the open loop
gain of the input buffer. But you get at least a better
common mode impedance (what would be adequate IMO)
> Short-circuit currents could pass through the
> transistors as before and ESD-currents would go to the
> reference amplifier.
>
> > Further you use one reference electrode. Do you
> > think this could be exchanged with the DRL output ?
>
> Could you please clarify what you mean? The reference
> is channel E0 in the biosemi-schematic
I was a bit confused, because I did not know, if the reference
port on your schematic was in or out-direction.
> and if it
> fails, the current flowing in or out of the positive
> input must go through the same safety circuitry as the
> other channels use.
>
> > BTW: Does the circuit really need +-6V or could it
> > be operated with -2/3V as the modularEEG ?
>
> It is supposed to be entirely passive. The threshold
> voltage is determined by the transistors alone so I
> don't see any reason why it should not.
My question was more intended to see, if the the whole
www.biosemi.com/publications/artikel7.htm circuit
"eegfig3.gif" works at low voltage.
> I've attached the new attempt.
> I hope this works better.
R7 will not really protect X1 because the (-) input could still be overloaded.
For what purpose are the 1nF C's C1..3 ? For shunting HF they
must be connected to a low-impedance node (what they are seemingly not)
I have also attached an input/user protection circuit for the INA114 based
amplifier:
Worst case current through any port should be ca. 40uA.
The common mode impedance of the protection diodes is enhanced
by the gain of the DRL circuit. The differential mode impedance
is not.
HF is shunted by the 100pF caps and C27 (10nF). These Caps are
important, because CMRR and guarding will only work at low frequencies.
With dimensioning the DRL I am not quite finished. I am currently
doing simulations to get a reasonable phase margin in the open loop
bode plot.
BTW: Do you have an idea how the PSPICE AMB equations for OP-amps looks like ?
(gain and three poles would be enough ...)
It seems to me that this could be done with the LAPLACE transform... or is this
only for transient analysis ?
Regards,
Joerg
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