protocol of BM

From: yaniv vilnai (yaniv_vi_at_yahoo.com)
Date: 2002-01-04 09:30:33

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hey
here's the protocol of BM . might be usefull .
again , does anybody have there software ?
Note: forwarded message attached.

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Hi Yaniv,

This is funny... i went to Tom Collura's website to get the
information for you... and it leads to a porn website:

Well, i have the files here, so i'll attach them.=20=20

> also do you know if i can get the bm osftware without buying the device ?=
=20

i don't know.=20=20

> establish ngo in the states .=20

Oh, i think that's a good idea. I always thought you needed to
set up a formal entity if you wanted to distribute the device.

Best regards,

Rob

----- Original Message -----=20
From: yaniv vilnai=20
To: Rob Sacks=20
Sent: Friday, January 04, 2002 3:04 AM
Subject: hi rob=20

hi rob .

how's life ?=20

i have a question to ask you : maybe you know the details of the brainmas=
ter communication protocol ?=20

if so please send them .

also do you know if i can get the bm osftware without buying the device ?=
=20

sincerly yaniv v.=20

p.s. about our status - modular eeg 2-6 channels , low cost , iec certifi=
ed , i think is in the last stages .=20

also we trying to find a volunteering lawyer to establish ngo in the stat=
es .=20

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"= > <META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2>Hi Yaniv,</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>This is funny... i went to Tom Collura's w= ebsite to=20 get the</FONT></DIV> <DIV><FONT face=3DArial size=3D2>information for you... and it leads to a p= orn=20 website:</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Well, i have the files here</FONT><FONT fa= ce=3DArial=20 size=3D2>, so i'll attach them.  </FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>> <FONT face=3D"Times New Roman" size= =3D3>also do=20 you know if i can get the bm osftware without buying the device ?=20 </FONT></FONT></DIV> <DIV> </DIV> <DIV><FONT face=3DArial size=3D2>i don't know.  </FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>> <FONT face=3D"Times New Roman" size= =3D3>establish=20 ngo in the states . </FONT></FONT></DIV> <DIV> </DIV> <DIV><FONT face=3DArial size=3D2>Oh, i think that's a good idea.  I al= ways=20 thought you needed to</FONT></DIV> <DIV><FONT face=3DArial size=3D2>set up a formal entity if you wanted to di= stribute=20 the device.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Best regards,</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Rob</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <BLOCKQUOTE=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LE= FT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV> <DIV=20 style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>Fro= m:</B>=20 <A title=3Dyaniv_vi_at_yahoo.com href=3D"mailto:yaniv_vi_at_yahoo.com">yaniv vi= lnai</A>=20 </DIV> <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A title=3Deditor_at_r...= org=20 href=3D"mailto:editor_at_realization.org">Rob Sacks</A> </DIV> <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, January 04, 2002 3:0= 4=20 AM</DIV> <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> hi rob </DIV> <DIV><BR></DIV> <P>hi rob .</P> <P>how's life ? </P> <P>i have a question to ask you : maybe you know the details of the=20 brainmaster communication protocol ? </P> <P>if so please send them .</P> <P>also do you know if i can get the bm osftware without buying the devic= e ?=20 </P> <P>sincerly yaniv v. </P> <P>p.s. about our status - modular eeg 2-6 channels , low cost , iec cert= ified=20 , i think is in the last stages . </P> <P>also we trying to find a volunteering lawyer to establish ngo in the s= tates=20 . </P> <P> </P> <P><BR> <HR SIZE=3D1> <B>Do You Yahoo!?</B><BR>Send your FREE holiday greetings online at <A=20 href=3D"http://rd.yahoo.com/mail_us/tag/?http://greetings.yahoo.com/">Yah= oo!=20 Greetings</A>.</BLOCKQUOTE></BODY></HTML>

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------=_NextPart_000_000A_01C194D0.29A6F300 Content-Type: text/plain; name="bm_11_asm.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="bm_11_asm.txt"

***** BM_11.ASM ************************************************ * ADC + Digital Input and Output Module for Brain Master Projcet * Lead by Thomas F. Collura Ph.D., P.E. *=20 * Written by and (c) W. Robert S. Webber Ph.D. CEng. MIEE *=20 * Squarey Basement Software *=20 * Date Wed 6 Sept 1995 *=20 * Copyright =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D *=20 * As with any freeware I would make no guarantee, warranty implied or * otherwise that the code is good for anything, will not harm anyone * however used. That is, what ever happens or does not happen as a * result of using or not using this code is not my fault or * responsibility.=20 *=20 * This program is licensed to Tom Collura and the Brain Master * project to be freely distributed as part of that project. *=20 * Any derived work would be the property and responsibility of the * person deriving such work. An acknowledgement of the original * source would be appreciated. *=20 * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 * Start of Genaral stuff =20 * From BUF32.ASM *************** * EQUATES * *************** RAMBS EQU $0000 start of ram =20 REGBS EQU $1000 start of registers =20 ROMBS EQU $E000 start of rom =20 STREE EQU $B600 start of eeprom ENDEE EQU $B7FF end of eeprom

PORTE EQU REGBS+$0A port E CFORC EQU REGBS+$0B force output compare TCNT EQU REGBS+$0E timer count TOC5 EQU REGBS+$1E oc5 reg =20 TCTL1 EQU REGBS+$20 timer control 1 TMSK1 EQU REGBS+$22 timer mask 1 TFLG1 EQU REGBS+$23 timer flag 1 TMSK2 EQU REGBS+$24 timer mask 2 =20 BAUD EQU REGBS+$2B sci baud reg SCCR1 EQU REGBS+$2C sci control1 reg SCCR2 EQU REGBS+$2D sci control2 reg SCSR EQU REGBS+$2E sci status reg SCDAT EQU REGBS+$2F sci data reg =20 BPROT EQU REGBS+$35 block protect reg OPTION EQU REGBS+$39 option reg COPRST EQU REGBS+$3A cop reset reg PPROG EQU REGBS+$3B ee prog reg HPRIO EQU REGBS+$3C hprio reg =20 CONFIG EQU REGBS+$3F config register =20 DFLOP EQU $4000 evb d flip flop =20 DUART EQU $D000 duart address PORTA EQU DUART PORTB EQU DUART+8 =20 ACIA EQU $9800 acia address =20 PROMPT EQU '>' BUFFLNG EQU 35 CTLA EQU $01 exit host or assembler CTLB EQU $02 send break to host CTLW EQU $17 wait CTLX EQU $18 abort DEL EQU $7F abort EOT EQU $04 end of text/table SWI EQU $3F =20 * End of section from BUF32.ASM =20 BUFISIT EQU $e00A * Cold Start for Buffalo after testing PE0 =20 TMP1 EQU $00C0 * For Buffalo for use with .HEXBIN SHFTREG EQU $009C * For Buffalo for use with .HEXBIN SHFTREG2 EQU $009D * For Buffalo for use with .HEXBIN =20 CTLQ EQU $11 * Ctrl/Q Restart i.e. DC1 CTLS EQU $13 * Ctrl/S CTLV EQU $16 * Used instead of Ctrl/S for Pause CTLD EQU $04 * Ctrl/D Stop Interrupts & Return to Buffalo CR_KEY EQU $0D * Carridge Return=20 =20 TFLG2 EQU REGBS+$25 Timer Flag 2 PACTL EQU REGBS+$26 Pulse Accumulator Control Reg =20 PORT_A EQU REGBS+$00 I/O Port A PORT_B EQU REGBS+$04 I/O Port B PORT_C EQU REGBS+$03 I/O Port C PORT_D EQU REGBS+$08 I/O Port D PORT_E EQU REGBS+$0A I/O Port E =20 PIOC EQU REGBS+$02 STAF STAI CWOM HNDS OIN PLS EGA INVB PORTCTL EQU REGBS+$05 DDRC EQU REGBS+$07 DDRD EQU REGBS+$09 =20 * ADC Registers ADCTL EQU REGBS+$30 ADC Control Register ADC_R1 EQU REGBS+$31 ADC Result 1 ADC_R2 EQU REGBS+$32 ADC Result 2 ADC_R3 EQU REGBS+$33 ADC Result 3 ADC_R4 EQU REGBS+$34 ADC Result 4 =20 * Relative Register Addresses wrt to REGBS =20 R_PORTE EQU $0A port E R_CFORC EQU $0B force output compare R_TCNT EQU $0E timer count R_TOC5 EQU $1E oc5 reg =20 R_TCTL1 EQU $20 timer control 1 R_TMSK1 EQU $22 timer mask 1 R_TFLG1 EQU $23 timer flag 1 =20 R_TMSK2 EQU $24 timer mask 2 R_TFLG2 EQU $25 Timer Flag 2 =20 R_PACTL EQU $26 Pulse Accumulator Control Reg =20 R_BAUD EQU $2B sci baud reg R_SCCR1 EQU $2C sci control1 reg R_SCCR2 EQU $2D sci control2 reg R_SCSR EQU $2E sci status reg R_SCDAT EQU $2F sci data reg =20 R_OPTION EQU $39 option reg =20 R_PORT_A EQU $00 Port A R_PORT_B EQU $04 Port B R_PORT_C EQU $03 Port C R_PORT_D EQU $08 Port D R_PORT_E EQU $0A Port E =20 R_PIOC EQU $02 STAF STAI CWOM HNDS OIN PLS EGA INVB R_PORTCTL EQU $05 R_DDRC EQU $07 R_DDRD EQU $09 =20 R_ADCTL EQU $30 ADC Control Register R_ADC_R1 EQU $31 ADC Result 1 R_ADC_R2 EQU $32 ADC Result 2 R_ADC_R3 EQU $33 ADC Result 3 R_ADC_R4 EQU $34 ADC Result 4 =20 * For ADC Channels 0 to 3 ADC_NORM03 EQU $00 ADC_MULT03 EQU $10 ADC_SCAN03 EQU $20 ADC_MULT03SCAN EQU $30 =20 * For ADC Cahnnels 4 to 7 ADC_NORM47 EQU $04 ADC_MULT47 EQU $14 ADC_SCAN47 EQU $24 ADC_MULT47SCAN EQU $34 =20 * RTI Clock Rate for PACTL bits RTI0, RTI1 Note DDRA7 is also set $80 * so that Port A bit 7 is an Output * Given as time periods RTI_4.10 EQU $80 RTI_8.19 EQU $81 RTI_16.38 EQU $82 RTI_32.77 EQU $83 * Given as Sampling Frequencies RTI_244Hz EQU $80 RTI_122Hz EQU $81 RTI_61Hz EQU $82 RTI_31Hz EQU $83 =20 * Entry points into Buffalo =20 .WARMST EQU $FF7C .BPCLR EQU $FF7F .RPRINT EQU $FF82 .HEXBIN EQU $FF85 .BUFFAR EQU $FF88 .TERMAR EQU $FF8B .CHGBYT EQU $FF8E .READBU EQU $FF91 .INCBUF EQU $FF94 .DECBUF EQU $FF97 .WSKIP EQU $FF9A .CHKABR EQU $FF9D =20 .UPCASE EQU $FFA0 .WCHEK EQU $FFA3 .DCHEK EQU $FFA6 .INIT EQU $FFA9 .INPUT EQU $FFAC .OUTPUT EQU $FFAF .OUTLHL EQU $FFB2 .OUTRHL EQU $FFB5 .OUTA EQU $FFB8 .OUT1BY EQU $FFBB .OUT1BS EQU $FFBE .OUT2BS EQU $FFC1 .OUTCRL EQU $FFC4 .OUTSTR EQU $FFC7 .OUTST0 EQU $FFCA .INCHAR EQU $FFCD .VECINT EQU $FFD0 =20 * End of Genaral stuff for the ADC Module =20 ADC_RDY EQU $80 =20 * ADC Status bits in ADC_EN ADC_RUN EQU $01 =20 **** Start of Jump Table for ADC Module for Brain Master ********** **** Program Starts here (Table of entry Points and Config values) org STREE * Start at base of EEPROM Block ($B600) jmp BUFISIT * In case PE0 is HIGH start Buffalo anyway =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 ADC_INIT0: jmp ADC_INIT * Cold Start the ADC Module =20 **** Tbale of Configuration Bytes ****************************** ADC_RATE: fcb RTI_122Hz * RTI Rate bits. Other Possible Values are: * RTI_244Hz RTI_122Hz RTI_61Hz RTI_31Hz = =20 * ADC Channel Enable bits in CHAN_EN CHAN_1 EQU $01 * Bit 0 =3D Chan 1 Enable ( ADC Input PE 0 ) CHAN_2 EQU $02 * Bit 1 =3D Chan 2 Enable ( ADC Input PE 1 ) CHAN_3 EQU $04 * Bit 2 =3D Chan 3 Enable ( ADC Input PE 2 ) CHAN_4 EQU $08 * Bit 3 =3D Chan 4 Enable ( ADC Input PE 3 ) CHAN_5 EQU $10 * Bit 4 =3D Chan 5 Enable ( ADC Input PE 4 ) CHAN_6 EQU $20 * Bit 5 =3D Chan 6 Enable ( ADC Input PE 5 ) CHAN_7 EQU $40 * Bit 6 =3D Chan 7 Enable ( ADC Input PE 6 ) CHAN_8 EQU $80 * Bit 7 =3D Chan 8 Enable ( ADC Input PE 7 ) =20 * CHAN_EN0: fcb CHAN_1+CHAN_2+CHAN_3+CHAN_4 CHAN_EN0: fcb CHAN_1 =20 =20 * Mode Enable Bits in ADC_MODE * Enable Code 00 Hex (0000 0000 Binary) SEND_00 EQU $01 * Allows code 00 to be sent, * else code 00 is changed to 01 before sending. =20 CRLF_ON EQU $02 * If set will send CR, LF before Reply Messages =20 * Sync Protocol 0 Overrides other Sync protocols SYNC_NONE EQU $04 * No Sync Byte (Only useful for one channel =20 * Sync Protocol 1 ( N Sync, 8-N Digital Input ) if SYNC_* clear SYNC_ALT EQU $08 * Bit 3 Sync Protocol 2, 8 Sync bits, 8 Dig Input = Alt SYNC_BOTH EQU $10 * Bit 4 Sync Protocol 3, 8 Sync bits, 8 Dig Input = Both

START_ADC EQU $20 * Bit 5 Start up with ADC Running, else Startup Pa= used SIG_ON EQU $40 * Bit 6 Enable Sign On Copyright Message MSG_ON EQU $80 * Bit 7 Enable Messages =20 NOT_PROT1 EQU SYNC_ALT+SYNC_BOTH =20 * ADC_MODE: fcb MSG_ON+SIG_ON+SYNC_ALT+CRLF_ON ADC_MODE: fcb SYNC_NONE+START_ADC =20 =20 PROT_1_CT: fcb 3 * Range 2 to 8 * Protocol 1 Shift count for Sync_Count and Digital Input ( i.e. Port C ) * PROT_1_CT is the number of Sync_Count bits. * The Sync_Count and Port C bits are assembled into D=3D(A:B) * Then this value is shifted left by ( 8 - PROT_1_CT ) bits. * This moves some of Port C bits into A * and some Sync_Count bits out of A. The result is what is left in A. * In other words ( 8 - PROT_1_CT ) is the number of Dig Input bits and=20 =20 =20 IDLE_PULSE: fcb 255 * Range 1 to 255 * Idle Pulse length in units of about 3.53 micro seconds. * For E Clock =3D 2MHz. A count of 255 is about 0.9 milli second. =20 =20 **** Table of Configurable Command Keys ****************************** * These key values may be replaced if desired. RESUME_KEY: fcb CTLQ * Resume ADC Character. Pause to Run State PAUSE_KEY: fcb CTLV * Pause ADC Character (Ints still on) Run to Pause St= ate STOP_KEY: fcb CTLD * Stop Character. Disable Interrupts Return to Buffal= o=20=20=20=20=20=20=20=20

=20 **** Messages Table ************************************************** * These messages may be over written if desired. But must NOT * be made Longer and must end with EOT. =20 M_ADC_PAUSE: fcc 'ADC_P' fcb EOT =20=20=20=20=20=20=20=20=20=20=20=20=20=20 M_ADC_STOP: fcc 'ADC_S' fcb EOT =20 M_ADC_RUN: fcc 'ADC_R' fcb EOT =20=20=20=20=20=20=20=20=20=20=20=20=20=20 =20=20=20=20=20=20=20=20=20=20=20=20=20 **** Cold Start the ADC Module ****************************** ADC_INIT: ldx #REGBS * Point to Register Base bset R_TMSK2,X $40 * Set Bit RTII =20=20 ldaa R_PACTL,X * Set RTI Rate anda $FC ora ADC_RATE staa R_PACTL,X

ldaa #$7E * Load Jump Instruction staa $00EB * and save Vection Table =20=20=20=20=20=20=20=20=20=20=20=20 ldd #ADC_ISR * Load ADC_ISR Address staa $00EC * and save Hi byte in Vection Table stab $00ED * and save Low byte in Vection Table =20 ldx #REGBS * Point to Register Base ldaa #$00 * Simple i/o on Port C CWOM=3D0 HNDS=3D0 staa R_PIOC,X=20 =20=20=20=20=20=20=20=20=20=20=20=20=20 ldaa #$00 * Set Port C Bits 0-7 In staa R_DDRC,X =20=20=20=20=20=20=20=20=20=20=20=20=20 ldaa ADC_MODE * Set up Sync Count Mask anda #NOT_PROT1 beq SET_SYNC1 ldaa #$FF bra SET_SYNC2 =20=20=20=20=20=20=20=20=20=20=20=20=20 SET_SYNC1: ldx #SYNC_MSK_TBL * Setup Sync Count Mask Value jsr GET_P1_SH * Get Protocol Sync Shift Count and add to = X ldaa $00,X =20=20=20=20=20=20=20=20=20=20=20=20=20 SET_SYNC2: staa SYNC_MSK=20=20=20=20=20=20=20=20=20=20=20=20 =20 ldy #ADC_MODE brclr $00,Y SIG_ON NO_SIG_ON ldx #M_SIGON bsr MSG_OUT =20=20=20=20=20=20=20=20=20=20=20=20=20 NO_SIG_ON: ldx #M_ADC_RUN bsr MSG_OUT =20=20=20=20=20=20=20=20=20=20=20=20=20 clr SYNC_CT * clear the ADC Sync Count =20=20=20=20=20=20=20=20=20=20=20=20=20 clra brclr $00,Y START_ADC GO_PAUSE ldaa #ADC_RUN GO_PAUSE: staa ADC_EN =20 cli * Enable Intrrupts =20=20=20=20=20=20=20=20=20 **** Poll Input for Command Keys ****************************** ADC_MON: ldx #ADC_MODE =20 * inc PORT_C * Debug Show we are in polling loop =20 jsr .INPUT cmpa STOP_KEY BEQ ADC_EXIT =20=20=20=20=20=20=20=20=20=20=20=20 cmpa PAUSE_KEY BEQ ADC_PAUSE =20=20=20=20=20=20=20=20=20=20=20=20 cmpa RESUME_KEY BEQ ADC_RESUME

cmpa #CR_KEY BEQ DIG_OUT =20 **** Still Here, Read as Hex and store in SHFTREG2 jsr .HEXBIN =20=20=20=20=20=20=20=20=20=20=20=20=20 * clr PORT_C * Debug Show we are in polling loop =20=20=20=20=20=20=20=20=20=20=20=20=20 bra ADC_MON =20=20=20=20=20=20=20=20=20=20=20=20=20 DIG_OUT: ldaa SHFTREG2 staa PORT_B bra ADC_MON =20=20=20=20=20=20=20=20=20=20=20=20=20 ADC_RESUME: ldx #M_ADC_RUN bsr MSG_OUT =20 clr SYNC_CT * clear the ADC Sync Count ldaa #ADC_RUN * Re-enable ADC staa ADC_EN bra ADC_MON =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 ADC_PAUSE: clr ADC_EN ldx #M_ADC_PAUSE bsr MSG_OUT bra ADC_MON =20=20=20=20=20=20=20=20=20=20=20=20=20 ADC_EXIT: sei * Set Interrupt Mask ON clr ADC_EN=20=20=20=20=20=20 ldx #REGBS * Point to Register Base bclr R_TMSK2,X $40 * Clear Bit RTII =20 ldx #M_ADC_STOP bsr MSG_OUT =20=20=20=20=20=20=20=20=20=20=20=20=20 jmp .WARMST * Return to Buffalo Monitor =20 **** Output Message only if enabled ************************ * X Must point to message on input MSG_OUT: ldy #ADC_MODE brclr 0,Y MSG_ON SKIP_MSG brset 0,Y CRLF_ON CRLF_MSG=20 =20=20=20=20=20=20=20=20=20=20=20=20=20 jsr .OUTST0 * No CR LF Before Message rts =20=20=20=20=20=20=20=20=20=20=20=20=20 CRLF_MSG: jsr .OUTSTR * Send CR LF before Message SKIP_MSG: rts =20 **** Get Protocol 1 Sync Count Shift Value in B & add to X ********* * B is PROT_1_CT in it on exit GET_P1_SH: ldab PROT_1_CT * Get Shift Count in B decb * Adjust from 1 base to Zero Base andb #$07 * Force into range 0 to 7 abx * Add to X rts =20 **** ADC Module Inrerrupt Service Routine ***************** * All Registers saved on Stack by Interrupt h/w in 68HC11 ADC_ISR: EQU * ldaa #$80 staa PORT_A * Show Start of ISR on Port A bit 7 =20=20=20=20=20=20=20=20=20=20=20=20=20 ldx #ADC_EN * Check if ADC Scan Enabled brset $00,X ADC_RUN ADC_ISR1 =20=20=20=20=20=20=20=20=20=20=20=20=20 ldab IDLE_PULSE IDLE: asla * do something decb bne IDLE * Loop till done bra END_ISR =20=20=20=20=20=20=20=20=20=20=20=20=20 ***** Send Sync Byte First ****************************** =20 ADC_ISR1: ldx #SYNC_CT * Point to ADC Sync Count =20=20=20=20=20=20=20=20=20=20=20=20=20 ldaa $00,X * Get Sync Count in A SYNC_SKP: inca * Step on to next Count anda SYNC_MSK * Check if actual bits used are <> 0 cmpa #$FF * Also skip Count 255 beq SYNC_SKP * as Protocol 2 would need to send a value for 256 (Digital In) but 256 is * zero in 8 bits and zero is not allowed. * Protocol 2 needs to send a sync byte for * every Digital input byte alternating. Since only odd values are used for * sync count, there nedds to be the same number of even Sync counts * where Digital Input is sent, hence skip 255 as 0 is also skipped. =20 tsta * Skip Sync Count =3D 0 for bits used = =20=20=20=20=20=20=20=20=20=20 bne SYNC_OK inca SYNC_OK: staa $00,X * Put back in main memory =20=20=20=20=20=20=20=20=20=20=20=20 ldx #ADC_MODE brset $00,X SYNC_NONE SYNC_P0 =20=20=20=20=20=20=20=20=20=20=20=20 brset $00,X SYNC_ALT SYNC_P2 brset $00,X SYNC_BOTH SYNC_P3 =20=20=20=20=20=20=20=20=20=20=20=20 * Sync Protocol 1 is: * PROT_1_CT =3D Number of bits of Sync_Count (Range 2 to 8) * ( 8 - PROT_1_CT ) bits of Digital input from Port C * Sync_Count that ramps up 1 to 2^PROT_1_CT - 1 incrmenting by one * for each scan of the ADC chans in the ADC_ISR. After max count * it goes back to 1.

ldab PORT_C * Get Input bits from Port C to B * D=3D(A:B)=3D Sync_Count : Digital_Input (Port_C) * b15.....b8 : b7................. b0 psha * Save on stack pshb

* This is a case statement where a jump is calculated ldx #SHIFT_N * Get Start of Shift Table in X bsr GET_P1_SH * Get Protocol Sync Shift Count & Add to X =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 pulb * recover D=3D(A:B)=3D Sync_Count:Port C pula jmp 0,X * Cross Fingers and Jump to Shift line =20=20=20=20=20=20=20=20=20=20=20=20 * Start of Shift line Shift PROT_1_CT No. No. * on D Value Sync Cnt Dig Inpu= t * =3D(A:B) Bits Bits SHIFT_N: nop * 6 1 2 6 asld * 6 2 2 6 asld * 5 3 3 5 asld * 4 4 4 4 =20=20=20=20=20=20=20=20=20=20=20=20 asld * 3 5 5 3 asld * 2 6 6 2 asld * 1 7 7 1 nop * 0 8 8 0 =20=20=20=20=20=20=20=20=20=20=20=20 bra ADC_ISR2

* Sync Protocol 3 is:=20 * Sync Count sent, all 8 bits every Sweep of ADC Chans * Range 1 to 254 in tseps of 1 (1,2,3,4,5, .. 253,254) * Sync count is never 0 or 255 * Digital Inputs sent every Sweep of ADC Chans SYNC_P3: bsr BYTE_OUT bra SEND_DIG =20=20=20=20=20=20=20=20=20=20=20=20 * Sync Protocol 2 is:=20 * If Sync Count is odd send Sync Count all 8 bits. * Range 1 to 253 in steps of 2. (1,3,5,7.. 251,253) * Note: an Even Sync Count is never sent. * Sync Count bit 0 is always set when set. * If Sync Count is even send Digital Input (Port C) all 8 bits. SYNC_P2: tab * save Sync count in B to test Bit 0 andb #$01 * Test if Sync Count is ODD bne ADC_ISR2 * Send Sync Count SEND_DIG: ldaa PORT_C * Else send Port C all 8 bits =20=20=20=20=20=20=20=20=20=20=20=20 ADC_ISR2: bsr BYTE_OUT * Send out the Sync Byte.

**** Start Scanning ADC Channels ************************************** SYNC_P0: lda #ADC_MULT03 * Set ADC to SCAN All 4 Channels (0 to 3) staa ADCTL * Start ADC on 4 Channels =20=20=20=20=20=20=20=20=20=20=20=20 ldaa CHAN_EN0 * Get enable Flags for Chans 0-3 in A bsr ADC_LOOP

lda #ADC_MULT47 * Set ADC to SCAN All 4 Channels (4 to 7) staa ADCTL =20=20=20=20=20=20=20=20=20=20=20=20 ldaa CHAN_EN0 * Get enable Flags for Chans 4-7 lsra * Shift to bits 0-3 in A lsra lsra lsra bsr ADC_LOOP=20=20=20=20=20=20=20=20=20=20=20=20 = =20 END_ISR: ldx #REGBS * Signal End of ISR to Real Time Clock bclr R_TFLG2,X $3F =20=20=20=20=20=20=20=20=20=20=20=20 clr PORT_A * Show End of ISR on Port A bit 7

rti * End of ISR

********************************************************************** * Sends byte in Reg A to SCI BYTE_OUT: pshb

* ldab #$02 * Debug * stab PORT_C * Debug =20=20=20=20=20=20=20=20=20=20=20=20 ldab ADC_MODE * Check if allowed to send $00 andb #SEND_00 bne B_OUT2 tsta bne B_OUT2 inca=20 =20=20=20=20=20=20=20=20=20=20=20=20 B_OUT2: ldab SCSR * Read sci status reg bitb #$80 * loop until tdre=3D1 beq B_OUT2 nop * mimic timing of Buffalo Output routine staa SCDAT * Send Byte out =20=20=20=20=20=20=20=20=20=20=20=20 * clr PORT_C * Debug =20=20=20=20=20=20=20=20=20=20=20=20 pulb rts =20=20=20=20=20=20=20=20=20=20=20=20 ********************************************************************** * Loop through 4 ADC Channels and test if each is enabled * Skip those that are not. * A, B, X all modified * A must be setup with Flag bits in low for positions (0-3) * for each of the channels to be sent out

ADC_LOOP: EQU * * ldab #$04 * Debug * stab PORT_C * Debug =20=20=20=20=20=20=20=20=20=20=20=20 staa CHAN_EN ldx #ADCTL ldab #$01 * Mask that is scanned through all channels =20=20=20=20=20=20=20=20=20=20=20=20 ADC_WAIT: brclr $00,X ADC_RDY ADC_WAIT

inx * Point X to ADC Results Registers =20=20=20=20=20=20=20=20=20=20=20=20 NEXT_ADC: EQU * * ldaa #$04 * Debug * staa PORT_C * Debug

tba * Get Chan Select Mask anda CHAN_EN * Test against Chan Enable Mask beq SKIP_CHAN=20 ldaa $00,X * Get ADC value for Enabled chan bsr BYTE_OUT * and Send it out

SKIP_CHAN: EQU * * clr PORT_C * Debug

inx * Point to next channel aslb * Shit Select mask to next channel cmpb #$10 * Test Mask if end of loop blt NEXT_ADC rts

**** Short Form Copy Right Message ****************************** = =20=20 M_SIGON: fcc 'BM_CR_WRSW&TFC'

fcb EOT=20=20=20=20=20=20=20=20=20=20=20=20=20

**** Table of Masks for Sync Count when < 8 bits used in count SYNC_MSK_TBL: fcb $03 * Shift 6 PROT_1_CT =3D 1 Sync 2 Dig In = 6 fcb $03 * Shift 6 PROT_1_CT =3D 2 Sync 2 Dig In = 6 fcb $07 * Shift 5 PROT_1_CT =3D 3 Sync 3 Dig In = 5 fcb $0F * Shift 4 PROT_1_CT =3D 4 Sync 4 Dig In = 4 =20=20=20=20=20=20=20=20=20=20=20=20=20=20 fcb $1F * Shift 3 PROT_1_CT =3D 5 Sync 5 Dig In = 3 fcb $3F * Shift 2 PROT_1_CT =3D 6 Sync 6 Dig In = 2 fcb $7F * Shift 1 PROT_1_CT =3D 7 Sync 7 Dig In = 1 fcb $FF * Shift 0 PROT_1_CT =3D 8 Sync 8 Dig In = 0 =20=20=20=20=20=20=20=20=20=20=20=20=20 **** RAM Table ******************************************************* org $0100 SYNC_CT: rmb 1 * ADC Sync Count Range 1 to 254 ADC_EN: rmb 1 * ADC Enable Flags Set Bit 0 =3D Run CHAN_EN: rmb 1 * ADC Channel Enables Bits 0-3 Only used

SYNC_MSK: rmb 1 * Mask to check Sync Count when < 8 bits used

**** end of File BM_11.ASM ****************************************

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ADC Module Ver 0.91 for Brain Master

Written by and (c) W. Robert S. Webber Ph.D. CEng. MIEE Squarey Basement Software

Date Wed 5 Jul 1995 BM_10.ASM Ver 0.90 Revised 6 Sept 1995 BM_11.ASM Ver 0.91

Copyright ======================================================== As with any freeware I would make no guarantee, warranty implied or otherwise that the code is good for anything, will not harm anyone however used. That is, what ever happens or does not happen as a result of using or not using this code is not my fault or responsibility.

This program is licensed to Tom Collura and the Brain Master project to be freely distributed as part of that project.

Any derived work would be the property and responsibility of the person deriving such work. An acknowledgement of the original source would be appreciated. =================================================================

Changes: New Equates added for Setting Sampling frequency

> * Given as Sampling Frequencies > RTI_244Hz EQU $80 > RTI_122Hz EQU $81 > RTI_61Hz EQU $82 > RTI_31Hz EQU $83

Replace line 228 in c:\ap2\68hc11\brain_m\BM_10.ASM < ADC_RATE: fcb RTI_8.19 * RTI Rate bits.

with lines 234-235 from c:\ap2\68hc11\brain_m\BM_11.ASM > ADC_RATE: fcb RTI_122Hz * RTI Rate bits. Other Possible Values are: > * RTI_244Hz RTI_122Hz RTI_61Hz RTI_31Hz

Replace line 248 in c:\ap2\68hc11\brain_m\BM_10.ASM < CRLF_ON EQU $04 * If set will send CR, LF before Reply Messages

with lines 255-258 from c:\ap2\68hc11\brain_m\BM_11.ASM > CRLF_ON EQU $02 * If set will send CR, LF before Reply Messages > > * Sync Protocol 0 Overrides other Sync protocols > SYNC_NONE EQU $04 * No Sync Byte (Only useful for one channel

After line 459 in c:\ap2\68hc11\brain_m\BM_10.ASM insert lines 470-471 from c:\ap2\68hc11\brain_m\BM_11.ASM > brset $00,X SYNC_NONE SYNC_P0 >

Replace line 521 in c:\ap2\68hc11\brain_m\BM_10.ASM < lda #ADC_MULT03 * Set ADC to SCAN All 4 Channels (0 to 3)

with line 533 from c:\ap2\68hc11\brain_m\BM_11.ASM > SYNC_P0: lda #ADC_MULT03 * Set ADC to SCAN All 4 Channels (0 to 3)

(0) The ADC module is a general purpose program for the 68HC11 that allows for analog data to be collected from the analog Port E and sent back via the serial port. In addition, digital data, as a continuous stream, can be read from Port C and sent back with the analog data. Digital data may be sent to the ADC Module and appears as output on Port B. In order to maintain sync with the ADC module, one or two sync bytes are sent at the start of ever channel scan. There are three protocols for the sync byte, depending on how much digital input data is needed and how often it is required.

(1.0) Sync Protocol 0 Is a simple mode for use with one ADC channel. If this protocol is selected then no Sync byte is sent. The Control task is still active so that the ADC Module can be paused, resumed and control can be returned to the Buffalo monitor (Added with BM_11.ASM Ver 0.91)

(1.1) Sync Protocol 1 One byte, sync and digital combined The sync byte is made up of two bit fields. The high field is the sync count itself, while the low field is the upper part of Port C, the digital input port. This protocol is enabled by clearing both bits SYNC_ALT ($08) and SYNC_BOTH ($10) in ADC_MODE (B608). The width of the sync count and hence the number of digital input bits can be varied by setting a value in PROT_1_CT (B609). The range of this value is 2 to 8 meaning the number of bits of sync count as follows:

PROT_1_CT No. No. Value Sync Cnt Dig Input (B609) Bits Bits Port C bits read & position in sync byte S = sync bit, D = Digital Input bit 2 2 6 SSDD DDDD 76 5432 Position of Port C bits

3 3 5 SSSD DDDD 7 6543

4 4 4 SSSS DDDD 7654

5 5 3 SSSS SDDD 765

6 6 2 SSSS SSDD 76 7 7 1 SSSS SSSD 7

8 8 0 SSSS SSSS

(2) Sync Protocol 2 One byte, sync and one byte digital inputs alternating. For this protocol the digital input is only sampled every other scan of the ADC channels. How ever the sync burned is still only one extra byte in the data stream Details are given in Sync Protocol 3.

(3) Sync Protocol 3 Two bytes, sync followed by digital input. These two protocols are very similar and are not described separately. The only difference is that in Protocol 2 the sync byte is sent on the first scan of the adc channels then alternates between sending the digital input port byte with the sync byte. Since this protocol alternates only odd values of sync are sent, i.e 01, 03, 05, etc .... Where the even sync count would have been, the digital input is sent. For protocol 3 both sync and digital input are sent for each sweep of the analog channels. For both protocols the sync count starts a 01 and goes up to 253 for protocol 2 and 254 for protocol 3. Sync count 255 is never used.

(4) ADC Commands There are 3 single byte commands and two multi byte commands for the ADC module.

Start ADC Module = G B603 Cr This starts the ADC Module program. Once started the ADC Module polls for commands while sending ADC & digital data back over the serial line.

RUN (or RESUME) = Ctrl Q This command Starts the ADC Module sending data over the serial line.

STOP = Ctrl D This command completely shuts down the ADC Module and returns controls to Buffalo

PAUSE = Ctrl Q This command Pauses the ADC Module. Interrupts are still enabled, but no serial data is sent. The ADC Module still polls for commands, so that digital outputs can be sent to port B.

Send ASCII Hex to digital output Port B = HH Cr HH is the ASCII Hex value ( 00 to FF ) to be sent to Port B

(5) Ports used on 68HC11

Port A bit 7 ADC ISR Activity bit. This is high While the ISR is active. It is set to 1 at the start of the ISR and set to 0 at the end.

Port B all bits used as digital output.

Port C all or some bits used as digital input

Port E Analog input. All 8 channels can be used.

(6) Example session showing control passed to and from ADC Module program:

Interactive session with ADC Module code showing Start up and transfer of control to the ADC module and returning control back to Buffalo Monitor.

The example is from an actual session where ASCII down load was started before cold boot and remained in effect for the whole session. All responses from the 68HC11 are shown as Hex with ASCII shown following ':'. Above each reply is a brief description of the action that caused the reply.

Start of Session Responce From ADC Module Cold Boot Sign On Message. Reply: 0D 0A 42 55 46 46 41 4C 4F 20 33 2E 32 20 28 69 6E 74 29 20 2D 20 42 69 74 20 55 73 65 72 20 46 61 73 74 20 46 72 69 65 6E 64 6C 79 20 41 69 64 20 74 6F 20 4C 6F 67 69 63 61 6C 20 4F 70 65 72 61 74 69 6F 6E : BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt. Reply: 0D 0A 3E : >

Send Ctrl V to get State of System Reply: 16 0D 0A : echo Ctrl V 0D 0A 57 68 61 74 3F : What? 0D 0A 3E : >

Send Ctrl D to get State of System Reply: 04 0D 0A : echo Ctrl D 0D 0A 57 68 61 74 3F : What? 0D 0A 3E : >

Start ADC Module by sending g b603 Reply: 67 20 62 36 30 33 : g b603 0D 0A 0D 0A 42 4D 5F 43 52 5F 57 52 53 57 26 54 46 43 : BM_CR_WRSW&TFC 0D 0A 41 44 43 5F 52 : ADC_R

ADC Module starts up in Pause Mode (Interrupts active but no data sent) ADC_R is always sent for both Startup in pause and running modes.

Send Pause Command Reply: 0D 0A 41 44 43 5F 50 : ADC_P

Send Run Commands Reply: 0D 0A 41 44 43 5F 52 : ADC_R

Data starts coming, Sync Byte followed by 3 channels of Analog data Sync Count is highest 3 bits of Sync Bytes. Lower 5 bits are Digital Input lines form Port C, Bits b7 to b3

20 50 50 50 40 50 50 50 60 50 50 50 etc ... 40 50 50 50 60 50 50 50 80 50 50 50

Pause Command Ctrl V Sent Reply: 0D 0A 41 44 43 5F 50 : ADC_P

Stop Command Ctrl D Sent Reply: 0D 0A 41 44 43 5F 53 : ADC_S 0D 0A 3E : > Now back in Buffalo Monitor

Restart ADC Module by sending g b603 Reply: 67 20 62 36 30 33 : g b603

0D 0A 0D 0A 42 4D 5F 43 52 5F 57 52 53 57 26 54 46 43 : BM_CR_WRSW&TFC 0D 0A 41 44 43 5F 52 : ADC_R

Send stop Ctrl D Command Reply: 0D 0A 41 44 43 5F 53 : ADC_S 0D 0A 3E : >

Now back in Buffalo Monitor

Send stop Ctrl D Command again Reply: 04 0D 0A : echo Ctrl D 0D 0A 57 68 61 74 3F : What? 0D 0A 3E : >

Press reset Button i.e. cold start Reply: 0D 0A 42 55 46 46 41 4C 4F 20 33 2E 32 20 28 69 6E 74 29 20 2D 20 42 69 74 20 55 73 65 72 20 46 61 73 74 20 46 72 69 65 6E 64 6C 79 20 41 69 64 20 74 6F 20 4C 6F 67 69 63 61 6C 20 4F 70 65 72 61 74 69 6F 6E : BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt: Reply: 0D 0A 3E : >

Send stop Ctrl D Command Reply: 04 0D 0A : echo Ctrl D 0D 0A 57 68 61 74 3F : What? 0D 0A 3E : >

End of session

(7) ADC States. The ADC Module can be in any of 5 states. Three of these are for the monitor and 2 are for the ADC Porgram itself. The monitor states are M0 to M2 and the ADC states are A0 and A1. A description of each state and how to test for it is given.

M0 No power. Send Ctrl V and get no responce in 10 msec, send CR get no responce in 10 msec.

M1 Initial power up state. (before Buffalo has received any serial data). On entry to this state, Buffalo sends its sign on messgae. To test for this state, send Ctrl V, no response in 10 msec, send CR, get responce: 0D 0A 3E : >

M2 Buffalo fully initilised. In this state a single CR will repeat the last command. This is unpredictable and may well start the ADC module if last command was G B603. To test for this state, send Ctrl V which will be echoed back. At this point send CR to complete the command. The ADC Module will respond with: 04 : Ctrl V 0D 0A 57 68 61 74 3F : What? 0D 0A 3E : >

A0 ADC Module program is active but paused. Interrupts are on, Port A bit 7 is pulsing, but no serial data is being sent. This state is tested by sending Ctrl V, to which ADC Module responds 0D 0A 41 44 43 5F 50 : ADC_P

A1 ADC Module program is active and serial data is being sent. This state can be detected by receiving an endless stream of characters. On the other hand one can send Ctrl V which will force it to state A0 and respond with ADC_P. If on the other hand Buffalo is running, the unit will respond by echoing Ctrl V.

(8) State transitions: M0 -> M1 Apply power M1 -> M2 send CR M2 -> A0 send g b603 and have bit 5, $20 clear in ADC_MODE (B608) M2 -> A1 send g b603 and have bit 5, $20 set in ADC_MODE (B608) A1 -> A0 send Ctrl V A0 -> A1 send Ctrl Q A0,A1 - > M2 send Ctrl D A0,A1,M1,M2 -> M0 pull power.

(9) ADC Modes, Configuration Options and code address: The 4 character hex value begining with "B..." at the start of each line is the location of the variable in EEPROM that may be modified. These addresses should not change as changes are made to the code

B606 ADC_RATE: fcb RTI_8.19 * RTI Rate bits (see .LST file). RTI_4.10 EQU $80 256 Samples/Sec RTI_8.19 EQU $81 128 Sample/Sec RTI_16.38 EQU $82 64 Samples/Sec RTI_32.77 EQU $83 32 Samples/Sec

B607 CHAN_EN0: fcb CHAN_1+CHAN_2+CHAN_3+CHAN_4 Any Combination of channels may be enabled 0001 CHAN_1 EQU $01 * Bit 0 = Chan 1 Enable ( ADC Input PE 0 ) 0002 CHAN_2 EQU $02 * Bit 1 = Chan 2 Enable ( ADC Input PE 1 ) 0004 CHAN_3 EQU $04 * Bit 2 = Chan 3 Enable ( ADC Input PE 2 ) 0008 CHAN_4 EQU $08 * Bit 3 = Chan 4 Enable ( ADC Input PE 3 ) 0010 CHAN_5 EQU $10 * Bit 4 = Chan 5 Enable ( ADC Input PE 4 ) 0020 CHAN_6 EQU $20 * Bit 5 = Chan 6 Enable ( ADC Input PE 5 ) 0040 CHAN_7 EQU $40 * Bit 6 = Chan 7 Enable ( ADC Input PE 6 ) 0080 CHAN_8 EQU $80 * Bit 7 = Chan 8 Enable ( ADC Input PE 7 )

Mode Enable Bits in ADC_MODE B608 ADC_MODE: fcb MSG_ON+SIG_ON+SYNC_ALT+CRLF_ON

SEND_00 EQU $01 * Allows code 00 to be sent, else code 00 is changed to 01 before sending.

CRLF_ON EQU $02 * If set will send CR, LF before Reply Messages (Note: This bit was $04 in BM_10 Ver 0.90)

SYNC_NONE EQU $04 * Bit 2 Sync Protocol 0, No Sync Byte sent. Only useful for one channel ( Added with BM_11 Ver 0.91)

Sync Protocol 1 ( N Sync, 8-N Digital Input ) if SYNC_* clear i.e. Bit 3 and Bit 4

SYNC_ALT EQU $08 * Bit 3 Sync Protocol 2, 8 Sync bits, 8 Dig Input Alternating

SYNC_BOTH EQU $10 * Bit 4 Sync Protocol 3, 8 Sync bits, 8 Dig Input Both

START_ADC EQU $20 * Bit 5 Start up with ADC Running, else Startup Paused.

SIG_ON EQU $40 * Bit 6 Enable Sign On Copyright Message Bit 7 must also be on for Sign On to to appear.

MSG_ON EQU $80 * Bit 7 Enable all reply messages

B609 PROT_1_CT: fcb 3 * Range 2 to 8 Protocol 1 Shift count for Sync_Count and Digital Input ( i.e. Port C ) PROT_1_CT is the number of Sync_Count bits. The Sync_Count and Port C bits are assembled into D=(A:B), then this value is shifted left by ( 8 - PROT_1_CT ) bits. this moves some of Port C bits into A and some Sync_Count bits out of A. The result is what is left in A. In other words ( 8 - PROT_1_CT ) is the number of Dig Input bits.

B60A IDLE_PULSE: fcb 255 * Range 1 to 255 Idle Pulse length in units of about 3.53 micro seconds. For E Clock 2MHz. A count of 255 is about 0.9 milli second. The pulse appears on Port A bit 7 when the Interrupt service routine (ISR) in active. When ADC Module is paused its length is goverened by this value. When the ADC Module is sending data, the pulse lenght is goverened by the amount of data to be sent for every sweep of the channels. The more the data, the longer the pulse.

(10) Table of Configurable Command Keys These key values may be replaced if desired.

B60B RESUME_KEY: fcb CTLQ * Run or Resume ADC Character. Pause to Run State

B60C PAUSE_KEY: fcb CTLV * Pause ADC Character (Ints still on) Run to Pause State

B60D STOP_KEY: fcb CTLD * Stop Character. Disable Interrupts and Return to Buffalo

(11) Messages Table. These messages may be over written if desired. But must NOT be made Longer and must end with EOT ($04). B60E M_ADC_PAUSE: fcc 'ADC_P' b613 fcb EOT

B614 M_ADC_STOP: fcc 'ADC_S' B619 fcb EOT

B61A M_ADC_RUN: fcc 'ADC_R' B61F fcb EOT

(12) Example Dumps of the ADC Module running. Each dump starts from when the ADC Module enters Run State A0 -> A1 i.e. it receives Ctrl Q:

Configuration is: Reply Responce Enabled 3 ADC channels Protocol 1, 5 Sync bits & 3 digital input bits (b7 to b5) from Port C in positions b2 to b0. Digital inputs are all 1s. Sync sent first ADC Channels 0D 0A 41 44 43 5F 52 0F 50 50 50 17 50 50 50 1F 50 50 50 27 50 50 50 2F 50 50 50 37 50 50 50 3F 50 50 50 47 50 50 50 4F 50 50 50 57 50 50 50 5F 50 50 50 67 50 50 50 6F 50 50 50 77 50 50 50 7F 50 50 50 87 50 50 50 8F 50 50 50 97 50 50 50 9F 50 50 50 A7 50 50 50 AF 50 50 50 B7 50 50 50 BF 50 50 50 C7 50 50 50 CF 50 50 50 D7 50 50 50 DF 50 50 50 E7 50 50 50 EF 50 50 50 F7 50 50 50 FF Sync rolls over 50 50 50 0F 50 50 50 17 50 50 50 1F 50 50 50 27 50 50 50 2F 50 50 50 37 50 50 50 3F 50 50 50 47 50 50 50 4F 50 50 50 57 50 50 50 5F 50 50 50 67 50 50 50 6F 50 50 50 77 50 50 50 7F 50 50 50 87

Configuration is: Reply Responce Enabled 3 ADC channels Protocol 1, 4 Sync bits & 4 digital input bits (b7 to b4) from Port C in positions b3 to b0. Digital inputs are all 1s. Sync sent first ADC Channels 0D 0A 41 44 43 5F 52 1F 50 50 50 2F 50 50 50 3F 50 50 50 4F 50 50 50 5F 50 50 50 6F 50 50 50 7F 50 50 50 8F 50 50 50 9F 50 50 50 AF 50 50 50 BF 50 50 50 CF 50 50 50 DF 50 50 50 EF 50 50 50 FF Sync rolls over 50 50 50 1F 50 50 50 2F 50 50 50 3F 50 50 50 4F 50 50 50 5F 50 50 50 6F 50 50 50 7F 50 50 50 8F 50 50 50 9F 50 50 50 AF 50 50 50 BF 50 50 50 CF 50 50 50 DF 50 50 50 EF 50 50 50 FF 50 50 50 1F Sync rolls over 50 50 50 2F 50 50 50 3F 50 50 50 4F 50 50 50 5F 50 50 50 6F 50 50 50 7F 50 50 50 8F 50 50 50 9F 50 50 50 AF 50 50 50 BF 50 50 50 CF 50 50 50 DF

Configuration is: Reply Responce Enabled 3 ADC channels Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C Alternating. Sync sent first then digital input = all 1s. 0D 0A 41 44 43 5F 52 01 50 50 50 FF 50 50 50 03 50 50 50 FF 50 50 50 05 50 50 50 FF 50 50 50 07 50 50 50 FF 50 50 50 09 50 50 50 FF 50 50 50 0B 50 50 50 FF 50 50 50 11 50 50 50 FF 50 50 50 13 50 50 50 FF 50 50 50 15 50 50 50 FF 50 50 50 17 50 50 50 FF 50 50 50 19 50 50 50 FF 50 50 50 1B 50 50 50 FF 50 50 50 1D 50 50 50 FF 50 50 50 1F etc ... 50 50 50 FF 50 50 50 F1 50 50 50 FF 50 50 50 F3 50 50 50 FF 50 50 50 F5 50 50 50 FF 50 50 50 F7 50 50 50 FF 50 50 50 F9 50 50 50 FF 50 50 50 FB 50 50 50 FF 50 50 50 FD 50 50 50 FF 50 50 50 01 Sync rolls over 50 50 50 FF 50 50 50 03 50 50 50 FF 50 50 50 05 50 50 50 FF 50 50 50 07 50 50 50 FF 50 50 50 09 50 50 50 FF 50 50 50 0B 50 50 50 FF 50 50 50 0D

Configuration is: Reply Responce Enabled 3 ADC channels Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C Alternating. Sync sent first then digital input = all 0s. Note: Although all Digital inputs are 0, the transmitted value has been incremented by 1 o avoid a value of 00. This feature can be disabled, i.e. allowing 00 to be transmitted by setting bit b0 in ADC_MODE (B608). 0D 0A 41 44 43 5F 52 01 50 50 50 01 50 50 50 03 50 50 50 01 50 50 50 05 50 50 4E 01 50 50 50 07 50 50 50 01 50 50 50 09 50 50 50 01 50 50 50 0B 50 50 50 01 50 50 50 0D 50 50 50 01 50 50 50 0F 50 50 50 01 50 50 50 11 50 50 50 01 50 50 50 13 50 50 50 01 50 50 50 15 4F 50 50 01 50 50 50 17 50 50 50 01 50 50 50 19 50 50 50 01 50 50 50 1B 50 50 50 01 50 50 50 1D 50 50 50 01 50 50 50 1F 50 50 50 01 50 50 50 21 50 50 50 01 50 50 50 23

Configuration is: Reply Responce Enabled 2 ADC channels Protocol 3, 8 Sync bits & 8 digital input bits (b7 to b3) Port C Both Sync sent first then digital input = all 1s. 0D 0A 41 44 43 5F 52 01 FF 50 50 02 FF 50 50 03 FF 50 50 04 FF 50 50 05 FF 50 50 06 FF 50 50 07 FF 50 50 08 FF 50 50 09 FF 50 50 0A FF 50 50 0B FF 50 50 0C FF 50 50 0D FF 50 50 0E FF 50 50 0F FF 50 50 10 FF 50 50 11 FF 50 50 12 FF 50 50 13 FF 50 50 14 FF 50 50 15 FF 50 50 16 FF 50 50 17 FF 50 50 18 FF 50 50 19 FF 50 50 1A FF 50 50 1B etc ... FF 50 50 F2 FF 50 50 F3 FF 50 50 F4 FF 50 50 F5 FF 50 50 F6 FF 50 50 F7 FF 50 50 F8 FF 50 50 F9 FF 50 50 FA FF 50 50 FB FF 50 50 FC FF 50 50 FD FF 50 50 FE FF 50 50 01 FF 50 50 02 FF 50 50 03 Sync Roll over FF 50 50 04 FF 50 50 05 FF 50 50 06 FF 50 50 07 FF 50 50 08 FF 50 50 09 FF 50 50 0A FF 50 50 0B FF 50 50 0C FF 50 50 0D FF 50 50 0E FF 50 50 0F tfcdev 15:

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