From: Jim Meissner (jpmeissner_at_mindspring.com)
Date: 2002-02-03 00:53:33
Dear Joerg:
I used a Mind Mirror for years and did not have this time constant problem that you are anticipating. They used either 10 or 100 uf capacitors. Usually you put the probes on the head first, then plug in the connector. There should not be any voltage transient. At most it would take 10 seconds orso to settle down to within a few microvolts.
By putting some back to back low leakage diodes ( like the 2N3904 BC diode ) across the 10 meg resistor, the settling time will be much faster.
The capacitor coupling eliminates the electrode offset voltage that you were worried about and also blocks any DC if the op amp were to fail to a rail. This also addresses the concerns the Mortz expressed.
Why don't you look at this more seriously.
With my design I had other reasons why I wanted the DC coupling throughout.
Juergen P. (Jim) Meissner
Check out my Website at www.MeissnerResearch.com
Read about the benefits of the Brain State Synchronizer sounds for improving your life and health.
----- Original Message -----
From: Joerg Hansmann
To: buildcheapeeg_at_yahoogroups.com
Sent: Friday, February 01, 2002 9:47 PM
Subject: Re: [buildcheapeeg] Re: Brainmaster input stage
Dear Jim:
----- Original Message -----
From: Jim Meissner <jpmeissner_at_mindspring.com>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Thursday, January 31, 2002 6:59 PM
Subject: Re: [buildcheapeeg] Re: Brainmaster input stage
Dear Joerg:
>> > So by inspecting the BrainMaster input stage, I guess at some low
>> > frequency the source resistance will be 10 Meg as the Xc of the
>> > 0.01 mf capacitor increases with lower frequencies. I wonder if
>> > you could try to simulate that stage again using larger capacitor
>> > values. I would be interested to see what capacitor value will
>> > give "good" noise down to 0.1 Hz? Somewhere I have the schematic
>> > for the original Mind Mirror. I think they used a 10 or 100 mf
>> > capacitors feeding into a discrete transistor for the lowest
>> > possible noise.
>
>Let's try this again. I am talking about the BrainMaster input stage. Your >schematic showed 0.01uf capacitors and a 10 meg to
ground.
>
>Would you be able to do a noise plot for various size capacitors.
>Let's say 1 uf, 10 uf, and 100 uf.
Yes. It was hard work (and I have some doubt that my modeling
solution is very elegant), but here it is (see picture).
The plot shows the rms noise voltage density that is produced by
the noise current flow from the AD620 input into the brainmaster
input hp network. (AD620 voltage noise not yet simulated)
I have included the 10nF plot on purpose, because this is the
original bm-design.
Here are the noise voltages (from integrating the voltage densities
over a frequency range from 0.1 to 100Hz):
10nF: 10.34 e-006 Vrms, 62 uVp-p noise, time constant=0.1 sec
100nF: 4.93 e-006 Vrms, 29.6 uVp-p noise, time constant=1.0 sec
1uF: 0.69 e-006 Vrms, 4.1 uVp-p noise, time constant= 10 sec
10uF: 0.072e-006 Vrms, 0.4 uVp-p noise, time constant=100 sec
With 10uF the noise current component becomes quite acceptable compared
with the AD620 voltage noise (RTI, G>=100) that is 0.28uVp-p for a
BW 0.1 to 10Hz.
However the R*C timeconstant is unacceptable high (100 seconds).
Just imagine you place the electrodes on your head and would have to
wait about 5 times the time constant (more than 8 minutes) until
the trace has settled.
>
>If the noise were "good" at 1 Hz what would it rise to at .1 Hz?
>
>For the moment please ignore the capacitor characteristics. Assume a perfect >capacitor for now.
Done.
>(BTW I worked for a capacitor manufacturer and there are many capacitor types >available, although some become very expensive.)
>
>Based on Andreas numbers, a 10 uf might be a compromise. I have some inexpensive 10 >uf metalized Mylar caps that should work
better than electrolytics.
If the problem with the time constant would not be present this could work.
The only way to get around this I can imagine at the moment could be a
FET switch parallel with R1 that gets switched into low impedance mode
for a few seconds by some logic or by software in order to reset a trace
with too much DC.
Regards,
Joerg
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