From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2002-03-08 23:21:59
Hi,
----- Original Message -----
From: sleeper75se <sleeper75se_at_yahoo.se>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Friday, March 08, 2002 8:34 PM
Subject: [buildcheapeeg] Re: Virtual Ground Questions
> Hi Joerg and Sar,
>
> I'm responding to your posts in a single message, to defragment the
> discussion a bit.
...
> --- In buildcheapeeg_at_yahoogroups.com, "Joerg Hansmann" <info_at_jhansmann.de> wrote:
>
> > A similar circuit is working quite well in the comEEG prototype.
> > However I must admit, that the testing level is quite low
> > (on the oscilloscope I could not see oscillations).
> > To be sure a more thorough test should be done with a function
> > generator that injects a square wave into the control loop.
> >
> > (any volunteers here with the right equipment ?)
>
> I have all the tools: a function generator, 2 channel 100MHz
> oscilloscope, minimum scale 2mV/div, and lab power. What are you
> lacking, the function generator,
The function generator.
> a better scope? Time? :-)
>
> If it is the function generator - how about using the output of a
> sound card as signal source? All you need is a pair of biasing
> resistors and possibly a capacitor at the opamp input. The resistors
> should form a good enough approximation of vref/2 since you are
> testing stability and not noise levels.
During tests of a software (SDL) port of Jim Meissner's synchronizer
I have looked at my soundcard output:
It has much ground noise (PC and scope both connected to protection
earth give a horrible ground loop ) and it has a nasty hp characteristic.
Perhaps I will do the testing with the 555 calibration signal output
(scaled to 1Vp-p or so)
> > IIRR the important trick in the virtual ground
> > circuit was the ESR of the tanatalum C at the output
> > of the op-amp. An ESR of about 500mOhms provided a
> > negative phase shift of about 90 degrees at the 0dB
> > point in the bode plot of the loop gain, resulting
> > in a total phase margin of about 90 degrees (what
> > is very stable)
>
> Hmm, then what is all the fuss about in textbooks and application
> notes
Perhaps a lack of information ?
> if you can fix the problem just by adding a large enough
> capacitor with low ESR?
Not low ESR but defined ESR. If the ESR gets too low the loop
gets unstable again.
A very good explanation of how the ESR improves the stability
can be found in "AN-1148.pdf" from National Semiconductor,
page 5 chapter "LDO Compensation using ESR"
(http://www.national.com/an/AN/AN-1148.pdf)
> Could it be that most applications that may
> be "exposed" to large capacitances, need to output varying voltage
> levels rather than DC, so a large cap would simply distort the signal
> too much?
If it is another application than stabilizing voltages (like rail splitters
and LDOs) a large tantalum C at the output of the amplifier will give you
a lowpass. It depends on your signal spectrum if this is acceptable or not.
Regards,
Joerg
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