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ADC Module Ver 0.91 for Brain Master

Written by and (c) W. Robert S. Webber Ph.D. CEng. MIEE
Squarey Basement Software

Date Wed 5 Jul 1995 BM_10.ASM Ver 0.90
Revised 6 Sept 1995 BM_11.ASM Ver 0.91

Copyright ========================================================
As with any freeware I would make no guarantee, warranty implied or
otherwise that the code is good for anything, will not harm anyone
however used. That is, what ever happens or does not happen as a
result of using or not using this code is not my fault or
responsibility. 

This program is licensed to Tom Collura and the Brain Master
project to be freely distributed as part of that project.

Any derived work would be the property and responsibility of the
person deriving such work. An acknowledgement of the original
source would be appreciated.
=================================================================

Changes:
New Equates added for Setting Sampling frequency

> * Given as Sampling Frequencies
> RTI_244Hz EQU $80
> RTI_122Hz EQU $81
> RTI_61Hz EQU $82
> RTI_31Hz EQU $83


Replace line 228 in c:\ap2\68hc11\brain_m\BM_10.ASM
< ADC_RATE: fcb RTI_8.19 * RTI Rate bits.

with lines 234-235 from c:\ap2\68hc11\brain_m\BM_11.ASM
> ADC_RATE: fcb RTI_122Hz * RTI Rate bits. Other Possible
Values are:
> * RTI_244Hz RTI_122Hz RTI_61Hz RTI_31Hz


Replace line 248 in c:\ap2\68hc11\brain_m\BM_10.ASM
< CRLF_ON EQU $04 * If set will send CR, LF before Reply
Messages

with lines 255-258 from c:\ap2\68hc11\brain_m\BM_11.ASM
> CRLF_ON EQU $02 * If set will send CR, LF before Reply
Messages
> 
> * Sync Protocol 0 Overrides other Sync protocols
> SYNC_NONE EQU $04 * No Sync Byte (Only useful for one
channel

After line 459 in c:\ap2\68hc11\brain_m\BM_10.ASM insert lines
470-471 from c:\ap2\68hc11\brain_m\BM_11.ASM
> brset $00,X SYNC_NONE SYNC_P0
> 


Replace line 521 in c:\ap2\68hc11\brain_m\BM_10.ASM
< lda #ADC_MULT03 * Set ADC to SCAN All 4 Channels
(0 to 3)

with line 533 from c:\ap2\68hc11\brain_m\BM_11.ASM
> SYNC_P0: lda #ADC_MULT03 * Set ADC to SCAN All 4 Channels
(0 to 3)


(0) The ADC module is a general purpose program for the 68HC11
that allows for analog data to be collected from the analog Port E
and sent back via the serial port. In addition, digital data, as a
continuous stream, can be read from Port C and sent back with the
analog data. Digital data may be sent to the ADC Module and appears
as output on Port B.
In order to maintain sync with the ADC module, one or two sync
bytes are sent at the start of ever channel scan. There are three
protocols for the sync byte, depending on how much digital input
data is needed and how often it is required.

(1.0) Sync Protocol 0 Is a simple mode for use with one ADC
channel. If this protocol is selected then no Sync byte is sent.
The Control task is still active so that the ADC Module can be
paused, resumed and control can be returned to the Buffalo monitor
(Added with BM_11.ASM Ver 0.91)

(1.1) Sync Protocol 1 One byte, sync and digital combined
The sync byte is made up of two bit fields. The high field is
the sync count itself, while the low field is the upper part of
Port C, the digital input port. This protocol is enabled by
clearing both bits SYNC_ALT ($08) and SYNC_BOTH ($10) in ADC_MODE
(B608). The width of the sync count and hence the number of digital
input bits can be varied by setting a value in PROT_1_CT (B609).
The range of this value is 2 to 8 meaning the number of bits of
sync count as follows:

PROT_1_CT No. No.
Value Sync Cnt Dig Input
(B609) Bits Bits Port C bits read & position in sync byte
S = sync bit, D = Digital Input bit
2 2 6 SSDD DDDD
76 5432 Position of Port C bits

3 3 5 SSSD DDDD
7 6543

4 4 4 SSSS DDDD
7654

5 5 3 SSSS SDDD
765

6 6 2 SSSS SSDD
76
7 7 1 SSSS SSSD
7

8 8 0 SSSS SSSS


(2) Sync Protocol 2 One byte, sync and one byte digital inputs
alternating. For this protocol the digital input is only sampled
every other scan of the ADC channels. How ever the sync burned is
still only one extra byte in the data stream Details are given in
Sync Protocol 3.

(3) Sync Protocol 3 Two bytes, sync followed by digital input.
These two protocols are very similar and are not described
separately. The only difference is that in Protocol 2 the sync byte
is sent on the first scan of the adc channels then alternates
between sending the digital input port byte with the sync byte.
Since this protocol alternates only odd values of sync are sent,
i.e 01, 03, 05, etc .... Where the even sync count would have been,
the digital input is sent. For protocol 3 both sync and digital
input are sent for each sweep of the analog channels. For both
protocols the sync count starts a 01 and goes up to 253 for
protocol 2 and 254 for protocol 3. Sync count 255 is never used.


(4) ADC Commands
There are 3 single byte commands and two multi byte commands
for the ADC module.

Start ADC Module = G B603 Cr
This starts the ADC Module program. Once started the ADC Module
polls for commands while sending ADC & digital data back over the
serial line.

RUN (or RESUME) = Ctrl Q
This command Starts the ADC Module sending data over the serial
line.

STOP = Ctrl D
This command completely shuts down the ADC Module and returns
controls to Buffalo

PAUSE = Ctrl Q
This command Pauses the ADC Module. Interrupts are still enabled,
but no serial data is sent. The ADC Module still polls for
commands, so that digital outputs can be sent to port B.

Send ASCII Hex to digital output Port B = HH Cr
HH is the ASCII Hex value ( 00 to FF ) to be sent to Port B




(5) Ports used on 68HC11

Port A bit 7 ADC ISR Activity bit. This is high While the ISR is
active. It is set to 1 at the start of the ISR and set to 0 at the
end.

Port B all bits used as digital output. 

Port C all or some bits used as digital input

Port E Analog input. All 8 channels can be used.



(6) Example session showing control passed to and from ADC Module
program:

Interactive session with ADC Module code showing Start up and
transfer of control to the ADC module and returning control back to
Buffalo Monitor.

The example is from an actual session where ASCII down load
was started before cold boot and remained in effect for the whole
session. All responses from the 68HC11 are shown as Hex with ASCII
shown following ':'. Above each reply is a brief description of
the action that caused the reply.

Start of Session
Responce From ADC Module Cold Boot Sign On Message.
Reply:
0D 0A 42 55 46 46 41 4C 4F 20 33 2E 32 20 28 69
6E 74 29 20 2D 20 42 69 74 20 55 73 65 72 20 46
61 73 74 20 46 72 69 65 6E 64 6C 79 20 41 69 64
20 74 6F 20 4C 6F 67 69 63 61 6C 20 4F 70 65 72
61 74 69 6F 6E :
BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt.
Reply:
0D 0A 3E : >

Send Ctrl V to get State of System
Reply:
16 0D 0A : echo Ctrl V
0D 0A 57 68 61 74 3F : What?
0D 0A 3E : >

Send Ctrl D to get State of System
Reply:
04 0D 0A : echo Ctrl D
0D 0A 57 68 61 74 3F : What?
0D 0A 3E : >

Start ADC Module by sending g b603
Reply:
67 20 62 36 30 33 : g b603
0D 0A
0D 0A 42 4D 5F 43 52 5F 57 52 53 57 26 54 46 43 :
BM_CR_WRSW&TFC
0D 0A 41 44 43 5F 52 : ADC_R

ADC Module starts up in Pause Mode (Interrupts active but no data
sent)
ADC_R is always sent for both Startup in pause and running modes.

Send Pause Command
Reply:
0D 0A 41 44 43 5F 50 : ADC_P

Send Run Commands
Reply:
0D 0A 41 44 43 5F 52 : ADC_R

Data starts coming, Sync Byte followed by 3 channels of Analog data
Sync Count is highest 3 bits of Sync Bytes.
Lower 5 bits are Digital Input lines form Port C, Bits b7 to b3

20 50 50 50
40 50 50 50
60 50 50 50
etc ...
40 50 50 50
60 50 50 50
80 50 50 50

Pause Command Ctrl V Sent
Reply:
0D 0A 41 44 43 5F 50 : ADC_P

Stop Command Ctrl D Sent
Reply:
0D 0A 41 44 43 5F 53 : ADC_S
0D 0A 3E : >
Now back in Buffalo Monitor

Restart ADC Module by sending g b603
Reply:
67 20 62 36 30 33 : g b603

0D 0A
0D 0A 42 4D 5F 43 52 5F 57 52 53 57 26 54 46 43 : BM_CR_WRSW&TFC
0D 0A 41 44 43 5F 52 : ADC_R

Send stop Ctrl D Command 
Reply:
0D 0A 41 44 43 5F 53 : ADC_S
0D 0A 3E : >

Now back in Buffalo Monitor

Send stop Ctrl D Command again
Reply:
04 0D 0A : echo Ctrl D
0D 0A 57 68 61 74 3F : What?
0D 0A 3E : >

Press reset Button i.e. cold start
Reply:
0D 0A 42 55 46 46
41 4C 4F 20 33 2E 32 20 28 69 6E 74 29 20 2D 20
42 69 74 20 55 73 65 72 20 46 61 73 74 20 46 72
69 65 6E 64 6C 79 20 41 69 64 20 74 6F 20 4C 6F
67 69 63 61 6C 20 4F 70 65 72 61 74 69 6F 6E :
BUFFALO 3.2 (int) - Bit User Fast Friendly Aid to Logical Operation

Send CR to Complete Start UP and Display Prompt:
Reply:
0D 0A 3E : >


Send stop Ctrl D Command
Reply:
04 0D 0A : echo Ctrl D
0D 0A 57 68 61 74 3F : What?
0D 0A 3E : >

End of session



(7) ADC States.
The ADC Module can be in any of 5 states. Three of these are for
the monitor and 2 are for the ADC Porgram itself. The monitor
states are M0 to M2 and the ADC states are A0 and A1. A description
of each state and how to test for it is given.

M0 No power. Send Ctrl V and get no responce in 10 msec, send CR
get no responce in 10 msec.

M1 Initial power up state. (before Buffalo has received any serial
data). On entry to this state, Buffalo sends its sign on messgae.
To test for this state, send Ctrl V, no response in 10 msec, send
CR, get responce:
0D 0A 3E : >

M2 Buffalo fully initilised. In this state a single CR will repeat
the last command. This is unpredictable and may well start the ADC
module if last command was G B603. To test for this state, send
Ctrl V which will be echoed back. At this point send CR to complete
the command. The ADC Module will respond with:
04 : Ctrl V
0D 0A 57 68 61 74 3F : What?
0D 0A 3E : >

A0 ADC Module program is active but paused. Interrupts are on, Port
A bit 7 is pulsing, but no serial data is being sent.
This state is tested by sending Ctrl V, to which ADC Module
responds
0D 0A 41 44 43 5F 50 : ADC_P

A1 ADC Module program is active and serial data is being sent. This
state can be detected by receiving an endless stream of characters.
On the other hand one can send Ctrl V which will force it to state
A0 and respond with ADC_P. If on the other hand Buffalo is running,
the unit will respond by echoing Ctrl V.

(8) State transitions:
M0 -> M1 Apply power
M1 -> M2 send CR
M2 -> A0 send g b603 and have bit 5, $20 clear in ADC_MODE (B608)
M2 -> A1 send g b603 and have bit 5, $20 set in ADC_MODE (B608)
A1 -> A0 send Ctrl V
A0 -> A1 send Ctrl Q
A0,A1 - > M2 send Ctrl D
A0,A1,M1,M2 -> M0 pull power.


(9) ADC Modes, Configuration Options and code address:
The 4 character hex value begining with "B..." at the start of each
line is the location of the variable in EEPROM that may be
modified. These addresses should not change as changes are made to
the code

B606 ADC_RATE: fcb RTI_8.19 * RTI Rate bits (see .LST file).
RTI_4.10 EQU $80 256 Samples/Sec
RTI_8.19 EQU $81 128 Sample/Sec
RTI_16.38 EQU $82 64 Samples/Sec
RTI_32.77 EQU $83 32 Samples/Sec


B607 CHAN_EN0: fcb CHAN_1+CHAN_2+CHAN_3+CHAN_4
Any Combination of channels may be enabled
0001 CHAN_1 EQU $01 * Bit 0 = Chan 1 Enable ( ADC Input PE 0 )
0002 CHAN_2 EQU $02 * Bit 1 = Chan 2 Enable ( ADC Input PE 1 )
0004 CHAN_3 EQU $04 * Bit 2 = Chan 3 Enable ( ADC Input PE 2 )
0008 CHAN_4 EQU $08 * Bit 3 = Chan 4 Enable ( ADC Input PE 3 )
0010 CHAN_5 EQU $10 * Bit 4 = Chan 5 Enable ( ADC Input PE 4 )
0020 CHAN_6 EQU $20 * Bit 5 = Chan 6 Enable ( ADC Input PE 5 )
0040 CHAN_7 EQU $40 * Bit 6 = Chan 7 Enable ( ADC Input PE 6 )
0080 CHAN_8 EQU $80 * Bit 7 = Chan 8 Enable ( ADC Input PE 7 )


Mode Enable Bits in ADC_MODE
B608 ADC_MODE: fcb MSG_ON+SIG_ON+SYNC_ALT+CRLF_ON

SEND_00 EQU $01 * Allows code 00 to be sent, else code 00 is 
changed to 01 before sending.

CRLF_ON EQU $02 * If set will send CR, LF before
Reply Messages
(Note: This bit was $04 in BM_10 Ver 0.90)

SYNC_NONE EQU $04 * Bit 2 Sync Protocol 0,
No Sync Byte sent. Only useful for one channel
( Added with BM_11 Ver 0.91)


Sync Protocol 1 ( N Sync, 8-N Digital Input ) if SYNC_* clear
i.e. Bit 3 and Bit 4


SYNC_ALT EQU $08 * Bit 3 Sync Protocol 2,
8 Sync bits, 8 Dig Input Alternating

SYNC_BOTH EQU $10 * Bit 4 Sync Protocol 3,
8 Sync bits, 8 Dig Input Both


START_ADC EQU $20 * Bit 5 Start up with ADC Running,
else Startup Paused.

SIG_ON EQU $40 * Bit 6 Enable Sign On Copyright Message
Bit 7 must also be on for Sign On to
to appear.

MSG_ON EQU $80 * Bit 7 Enable all reply messages


B609 PROT_1_CT: fcb 3 * Range 2 to 8
Protocol 1 Shift count for Sync_Count and Digital Input ( i.e. Port
C ) PROT_1_CT is the number of Sync_Count bits.
The Sync_Count and Port C bits are assembled into D=(A:B), then
this value is shifted left by ( 8 - PROT_1_CT ) bits.
this moves some of Port C bits into A and some Sync_Count bits out
of A. The result is what is left in A. In other words ( 8 -
PROT_1_CT ) is the number of Dig Input bits.



B60A IDLE_PULSE: fcb 255 * Range 1 to 255
Idle Pulse length in units of about 3.53 micro seconds.
For E Clock 2MHz. A count of 255 is about 0.9 milli second.
The pulse appears on Port A bit 7 when the Interrupt service
routine (ISR) in active. When ADC Module is paused its length is
goverened by this value. When the ADC Module is sending data, the
pulse lenght is goverened by the amount of data to be sent for
every sweep of the channels. The more the data, the longer the
pulse.



(10) Table of Configurable Command Keys
These key values may be replaced if desired.

B60B RESUME_KEY: fcb CTLQ * Run or Resume ADC Character.
Pause to Run State

B60C PAUSE_KEY: fcb CTLV * Pause ADC Character (Ints still on)
Run to Pause State

B60D STOP_KEY: fcb CTLD * Stop Character. Disable Interrupts and
Return to Buffalo



(11) Messages Table. These messages may be over written if desired.
But must NOT be made Longer and must end with EOT ($04).
B60E M_ADC_PAUSE: fcc 'ADC_P'
b613 fcb EOT

B614 M_ADC_STOP: fcc 'ADC_S'
B619 fcb EOT

B61A M_ADC_RUN: fcc 'ADC_R'
B61F fcb EOT




(12) Example Dumps of the ADC Module running. Each dump starts from
when the ADC Module enters Run State A0 -> A1 i.e. it receives
Ctrl Q:

Configuration is:
Reply Responce Enabled
3 ADC channels 
Protocol 1, 5 Sync bits & 3 digital input bits (b7 to b5)
from Port C in positions b2 to b0.
Digital inputs are all 1s.
Sync sent first ADC Channels
0D 0A 41 44 43 5F 52 0F 50 50 50 17 50 50 50 1F
50 50 50 27 50 50 50 2F 50 50 50 37 50 50 50 3F
50 50 50 47 50 50 50 4F 50 50 50 57 50 50 50 5F
50 50 50 67 50 50 50 6F 50 50 50 77 50 50 50 7F
50 50 50 87 50 50 50 8F 50 50 50 97 50 50 50 9F
50 50 50 A7 50 50 50 AF 50 50 50 B7 50 50 50 BF
50 50 50 C7 50 50 50 CF 50 50 50 D7 50 50 50 DF
50 50 50 E7 50 50 50 EF 50 50 50 F7 50 50 50 FF Sync rolls over
50 50 50 0F 50 50 50 17 50 50 50 1F 50 50 50 27
50 50 50 2F 50 50 50 37 50 50 50 3F 50 50 50 47
50 50 50 4F 50 50 50 57 50 50 50 5F 50 50 50 67
50 50 50 6F 50 50 50 77 50 50 50 7F 50 50 50 87


Configuration is:
Reply Responce Enabled
3 ADC channels 
Protocol 1, 4 Sync bits & 4 digital input bits (b7 to b4)
from Port C in positions b3 to b0.
Digital inputs are all 1s.
Sync sent first ADC Channels
0D 0A 41 44 43 5F 52 1F 50 50 50 2F 50 50 50 3F
50 50 50 4F 50 50 50 5F 50 50 50 6F 50 50 50 7F
50 50 50 8F 50 50 50 9F 50 50 50 AF 50 50 50 BF
50 50 50 CF 50 50 50 DF 50 50 50 EF 50 50 50 FF Sync rolls over
50 50 50 1F 50 50 50 2F 50 50 50 3F 50 50 50 4F
50 50 50 5F 50 50 50 6F 50 50 50 7F 50 50 50 8F
50 50 50 9F 50 50 50 AF 50 50 50 BF 50 50 50 CF
50 50 50 DF 50 50 50 EF 50 50 50 FF 50 50 50 1F Sync rolls over
50 50 50 2F 50 50 50 3F 50 50 50 4F 50 50 50 5F
50 50 50 6F 50 50 50 7F 50 50 50 8F 50 50 50 9F
50 50 50 AF 50 50 50 BF 50 50 50 CF 50 50 50 DF


Configuration is:
Reply Responce Enabled
3 ADC channels 
Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C
Alternating. Sync sent first then digital input = all 1s.
0D 0A 41 44 43 5F 52 01 50 50 50 FF 50 50 50 03
50 50 50 FF 50 50 50 05 50 50 50 FF 50 50 50 07
50 50 50 FF 50 50 50 09 50 50 50 FF 50 50 50 0B
50 50 50 FF 50 50 50 11 50 50 50 FF 50 50 50 13
50 50 50 FF 50 50 50 15 50 50 50 FF 50 50 50 17
50 50 50 FF 50 50 50 19 50 50 50 FF 50 50 50 1B
50 50 50 FF 50 50 50 1D 50 50 50 FF 50 50 50 1F
etc ...
50 50 50 FF 50 50 50 F1 50 50 50 FF 50 50 50 F3
50 50 50 FF 50 50 50 F5 50 50 50 FF 50 50 50 F7
50 50 50 FF 50 50 50 F9 50 50 50 FF 50 50 50 FB
50 50 50 FF 50 50 50 FD 50 50 50 FF 50 50 50 01 Sync rolls over
50 50 50 FF 50 50 50 03 50 50 50 FF 50 50 50 05
50 50 50 FF 50 50 50 07 50 50 50 FF 50 50 50 09
50 50 50 FF 50 50 50 0B 50 50 50 FF 50 50 50 0D



Configuration is:
Reply Responce Enabled
3 ADC channels 
Protocol 2, 8 Sync bits & 8 digital input bits (b7 to b0) Port C
Alternating. Sync sent first then digital input = all 0s.
Note: Although all Digital inputs are 0, the transmitted value
has been incremented by 1 o avoid a value of 00. This feature
can be disabled, i.e. allowing 00 to be transmitted by setting 
bit b0 in ADC_MODE (B608).
0D 0A 41 44 43 5F 52 01 50 50 50 01 50 50 50 03
50 50 50 01 50 50 50 05 50 50 4E 01 50 50 50 07
50 50 50 01 50 50 50 09 50 50 50 01 50 50 50 0B
50 50 50 01 50 50 50 0D 50 50 50 01 50 50 50 0F
50 50 50 01 50 50 50 11 50 50 50 01 50 50 50 13
50 50 50 01 50 50 50 15 4F 50 50 01 50 50 50 17
50 50 50 01 50 50 50 19 50 50 50 01 50 50 50 1B
50 50 50 01 50 50 50 1D 50 50 50 01 50 50 50 1F
50 50 50 01 50 50 50 21 50 50 50 01 50 50 50 23

Configuration is:
Reply Responce Enabled
2 ADC channels 
Protocol 3, 8 Sync bits & 8 digital input bits (b7 to b3) Port C
Both Sync sent first then digital input = all 1s.
0D 0A 41 44 43 5F 52 01 FF 50 50 02 FF 50 50 03
FF 50 50 04 FF 50 50 05 FF 50 50 06 FF 50 50 07
FF 50 50 08 FF 50 50 09 FF 50 50 0A FF 50 50 0B
FF 50 50 0C FF 50 50 0D FF 50 50 0E FF 50 50 0F
FF 50 50 10 FF 50 50 11 FF 50 50 12 FF 50 50 13
FF 50 50 14 FF 50 50 15 FF 50 50 16 FF 50 50 17
FF 50 50 18 FF 50 50 19 FF 50 50 1A FF 50 50 1B
etc ...
FF 50 50 F2 FF 50 50 F3 FF 50 50 F4 FF 50 50 F5
FF 50 50 F6 FF 50 50 F7 FF 50 50 F8 FF 50 50 F9
FF 50 50 FA FF 50 50 FB FF 50 50 FC FF 50 50 FD
FF 50 50 FE FF 50 50 01 FF 50 50 02 FF 50 50 03 Sync Roll over
FF 50 50 04 FF 50 50 05 FF 50 50 06 FF 50 50 07
FF 50 50 08 FF 50 50 09 FF 50 50 0A FF 50 50 0B
FF 50 50 0C FF 50 50 0D FF 50 50 0E FF 50 50 0F
tfcdev 15: