From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2001-12-21 12:12:00
Hi,
----- Original Message -----
From: sademade <sademade_at_yahoo.com>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Thursday, December 20, 2001 11:24 AM
Subject: [buildcheapeeg] Re: modularEEG input stage prototype ... Some Amp sec Questions :
...
> Q2: are the blue outlines over the original rs232eeg board
> for copper-box-shielding the amp-sections from 60 Hz, similar
> to many commercial PC A/D cards that otherwise would suffer
> from too much noise ... ?
No. It is much more low-end: Simple copper pouring areas
not displayed after loading.
I assume you have displayed the files with EAGLE ?
After loading a pcb-file always perform a "ratsnest" command
to get properly displayed copper pouring areas.
> Q3: Is there any realistic way to get low-noise enough design without
> the copper/nickel plated shieldboxes ?
Yes. The RS232EEG had about 1uVp-p noise with a copper foil
1 cm below it connected to VREF/2 and only single sided pcb.
...
> Q5: Could you please let me know what is your favorite book or
> resource for learning analog shielding/grounding/guarding techniques
> and their optimal PCB layout techniques,
In some datasheets of hi-res ADC this topic is covered partially.
What do you think of compiling a list rules / hints for
proper lo-noise lo-EMI layout ?
Some of them without special order:
*) Avoid trace loops (they are antennas and couple magnetically
into nearby traces)
*) Use lo-impedance GND (best a complete GND-plane)
*) Use low impedance GND on connectors (e.g. on a ribbon cable use
every 2nd wire for GND)
*) If split AGND/DGND-planes are used, connect them with low with
trace beneath the ADC
*) Properly bypass supply lines and AGND/Ref-Voltage.
Connect supply bypass Cs as short as possible.
Use star topology at bypass C.
*) Use star topology for signal return path (to avoid voltage drop
produced by the current of other stages)
*) For uV DC be aware of thermo-couples and temperature gradients over
different metals (e.g. connectors).
*) limit the BW of each stage as far as possible.
*) Do not route sensitve analog lines below or near digital logic or uC
I am sure there are much more rules / guidelines that I forgot
or not even know. Feel free to add/correct/comment/ complete the above.
Regards,
Joerg
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