From: sademade (sademade_at_yahoo.com)
Date: 2001-12-22 05:54:17
> After loading a pcb-file always perform a "ratsnest" command
> to get properly displayed copper pouring areas.
Thank You for the hint. That apparenty was the problem, as
did not grasp what those were, they could have been an outline
for a copper shield, and in a way, should have figured out it
was a copper-pour, but have never used Eagle before, protel
shows the pours ok always. Alzherimer does not come alone, too
bad it is trying to come too early, that is partially why
have interest in the EEG, to research what is different with
those who are still fast and coherent, compared to those who
are declining ( m. ) compared to past version of the same.
> Yes. The RS232EEG had about 1uVp-p noise with a copper foil
> 1 cm below it connected to VREF/2 and only single sided pcb.
So, would not this be a good reason for 2 layer with copper
pour on top, could not the same be achieved that way ?
> What do you think of compiling a list rules / hints for
> proper lo-noise lo-EMI layout ?
> Some of them without special order:
That would be awesome, if someones could do that, as
want to learn of those, have too long stayed with
mostly digital designs, and bailed out of analog parts
with choosing good parts, and religiosly aping the manufacturers'
suggestions, but need to learn to do it without them, so thankful
for your help !
> *) Avoid trace loops (they are antennas and couple magnetically
> into nearby traces)
Especially in analog apparently, and same with high-speed
digital, unless loops are really small in area, as per
mr maxwell ?
> *) Use lo-impedance GND (best a complete GND-plane)
Here, doesn't the distance between the layers have great
effect on the impedance of the signal return trough GND
at least on higher frequencies. Now, as this is low freq
design, can one forget the high frequency noise design
concepts, as they should not necessarily affect on low
freqs ...
In high freq designs, just choice bypass of capacitor type
and it's routing can make massive difference in the overall
path impedance ... what kind of analogical concepts is there
on low speed analog to take note of ?
> *) Use low impedance GND on connectors (e.g. on a ribbon cable use
> every 2nd wire for GND)
Twisted-pair as in some nice fancy twisted flat cables ?
> *) If split AGND/DGND-planes are used, connect them with low with
> trace beneath the ADC
Have done that religiosly, as per the manuf. app notes, apparently
this confines the currents where they need to, howabout when some
app notes recommend using an inductor to connect the power to the
adc, and sometimes, a resistor or inductor to connect the ground
planes, as per some kind of filtering ... should work, as the
currents are quite low, but apparently inductances must be very
low in this case ?
> *) Properly bypass supply lines and AGND/Ref-Voltage.
Here, the traces apparently must be as short as possible,
very short distance, and to planes, if possible, some
people claim double thin traces are even better, than one,
but, how about types of caps to use, and is there any
difference in types of vias, if one uses vias to power
planes ?
> Connect supply bypass Cs as short as possible.
> Use star topology at bypass C.
This is apparently the analog related important rule here ?
Have done this, but solid explanations, other than potential
differences, has not been explained, and as analog currents
are very very small, that explanation did not sound always
the best, so there must be other explanations, that are important,
too ?
> *) Use star topology for signal return path (to avoid voltage drop
> produced by the current of other stages)
But aren't the currents extra small, are they enough to require
the star-top ?
What if one uses plane, what makes it undesireable ?
Have tended to use planes, and they seemed to work well,
where did I go wrong because using planes ?
> *) For uV DC be aware of thermo-couples and temperature gradients
>ver different metals (e.g. connectors).
This has happened, and even fingerprints once almost destroyed
one circuitry from working at all ... what kind of soldering and
materials/techniques are recommended here to avoid the contact
potential troubles ... is any tin better than other, for example
silver-tin over lead-tin ?
> *) limit the BW of each stage as far as possible.
This sounds very sensible for analog, how can one prevent
60 Hz and RF from being induced to the circuitry, or is
the bandpass filtering getting rid of their effects well
enough to allow avoiding the copper/nickel caging, or could
such caging provide another decade of performance gains ?
> *) Do not route sensitve analog lines below or near digital logic
>r uC
Well, even a mostly digital-only and power-electronic man knew
that, have often used a sequential structure first analog, then
digital, and then power last, and using the thin narrow links
between the various ground planes, but, yet, would like to learn
really the thing also some concrete way, yet without having to
mix Mr. Fourier and Maxwell too deep, but that sounds impossible,
doesn't it.
Would like to find a program that could sim these, so that one
could tell before building the board if it is going to be good
or not. Too bad such are not available for reqular mortals.
> I am sure there are much more rules / guidelines that I forgot
> or not even know. Feel free to add/correct/comment/ complete the >a
Well, as am not good with this area, mostly more questions are coming
from this direction, and especially of how to understand and design
the shieldings, know that shieldings should be connected only in
one end to prevent the current loop from forming, but there are
some wieird shielding that use capacitive grounding at the other
end, and the active shielding would like to understand better
what when and why, and how.
Thanks a Million, Sade M.
This archive was generated by hypermail 2.1.4 : 2002-07-27 12:28:35 BST