From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2002-01-22 20:45:19
Dear Jim and all,
----- Original Message -----
From: Jim Meissner <jpmeissner_at_mindspring.com>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Sunday, January 20, 2002 5:59 AM
Subject: Re: [buildcheapeeg] virtual ground problem
>Dear Joerg:
>
>I hope you don't think that I am trying to argue with
>you. I am sharing similar experiences I have had in the
>past and how I solved them. It is meant to be helpful.
>
>I believe that having all the grounds, digital, analog,
>shield, and case at the same potential ( Star Ground ),
>is a must. I will go to great length to make that
>possible. ( Including separate batteries if needed )
This is the "classical" design and I have used
it in other projects with good results too.
However the "modern" way of designing seems to have
strong tendencies to single supply 5V or even less,
rail to rail (or at least single rail like the TLC272
or 277) op amps and ADCs.
Some years ago ADCs required +-5V supply. Modern
delta sigma ADCs like ADS1211 or ADS1252 however
use single +5V supply and have an input range of
0..4V.
So why not use this modern design paradigm ?
>When a system has a large gain such as looking at 0.1
>microvolts, it is easy get positive feedback loops and
>oscillations. Ground loops and power supply rails are
>the main source of feedback. Modern op amps with their
>great power supply rejection ratios have made us
>complacent.
Because I know, that the opamp-manufacturer provides
the high supply voltage rejection ratio there is no
room for being complacent. However I try to use the
features of the opamps and one of them definitely is the
high SVR.
>I have designed with tubes and discrete
>transistors and learned the hard way.
Designing with almost no inherent power supply rejection
must have been very difficult. I fully acknowledge this.
>The "redesign" should not be that difficult. Take
>"most" of the V/2 lines and put them on ground. Un-
>ground a few op amp power supply pins and run to the - 3
>volt buss. Put a low dropout regulator from the + 5
>Volt digital power to generated + 3 volts. Run a 7660 or
>such from the + 3 volt analog power to generate a -
>3volts.
>
>I do not know exactly which version you are working on
>so this is a general type comment. If could tell me
>which file to look at, I would be happy to be more
>precise.
The current modular EEG design can be found on the
sourceforge site.
I will post the new *.brd and *.sch files when the redesign
(see below) is done.
>
>On the other hand, you state that you do not like
>negative voltages. Even though I disagree with your
>viewpoint, I will make some suggestion if you want to
>stay with the present design.
>
>First you have to have a heavily bypassed + 5 volt
>digital power buss. It takes several types of
>capacitors to do that. I notice that you use a 47 uf
>and a 100 nf. What I like to see is a 100 uf high
>frequency electrolytic,
I do not know the properties of high frequency electrolytics.
Are they "better" than tantalum types ?
What ESR and serial inductivity do they have ?
>with a 10 uf tantalum and
>several 100 nf caps. As you know the physical placement
>and lead length and a good ground plane is important.
>Then I would look at the split voltage of 2.5 volts or
>V/2 from a different perspective. Try to make the
>impedance from this V/2 buss to the ground plane as low
>as possible. Put a 100 uf, 10 uf, 100 nf combination
>from the V/2 to the ground plane.
Multiple capacitors parallel will behave like resonant
circuits (due to their low ESR and an inductivity of about
10nH or more) unless they are dampened with little Rs
in series (see pictures "vgnd_Cs.png" vs. "vgnd_RCs.png")
However this is only simulation and I definiteley do not
have a networkanalyzer to verify the simulation results.
In the last days I have done many simulations
of circuits that could provide Vref/2:
1)virtual ground rail splitter TLE2426 from TI,
2)an enhanced version of my old design with the TLC272 opamp
(see picture "vgnd_TLC272_with_RCs.png")
and
3)the dual voltage LDO regulator TPS70102 (see picture
"dual voltage ldo TPS70102.png") from the datasheet).
...
>Try to
>use a low drop out regulator chip to drive the + 2.5
>volt buss from the + 5 volts. That way it thinks it is
>a 2.5 volt power supply and will be happy.
...
With properly dimensioned and selected components the TLE2426
and the TPS70102 did not seem to be superior to the low-cost
TLC272 solution. Of course the TLE2426 or the TPS70102 can deliver
much more current, but this feature is not needed in the modularEEG.
>This of course is a
>terrible load for the centering op amp or a "rail
>splitter".
Properly dimensioned the op amp will not be burdened
very much.
>I does not have enough drive current to move
>such a high capacitive load and will oscillate.
That is not the primary reason for oscillation.
National Semiconductor has written a very good
Application Note (AN-1148.pdf)
"Linear Regulators: Theory Of Operation and Compensation"
that explains why and when regulators oscillate
or show poor performance like ringing or impedance peaking.
In short the reason for oscillation or ringing
is too low phase margin at 0dB in the (open) loop
gain bode plot.
The method of compensation I use in the redesigned TLC272
rail splitter is the same as explained in the chapter:
"LDO Compensation using ESR".
By using a tantalum capacitor with a defined ESR of about
500mOhms to 1 Ohm a "Zero" or a high-pass element is
included in the feedback loop, that provides the necessary
phase reserve.
>Whether to regulate the + analog power supply line is
>another matter. I think at least there should be a
>resistor and another capacitor network just for the
>analog + volt buss. You do not want digital noise on
>the analog power buss.
I will use 2 separate LDOs, one for +5V digital, and one for
+5V analog.
>Hopefully this is of some help.
You have made me rethink my design and I have learned
a lot about capacitors, LDOs and stability.
Regards,
Joerg
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