From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2002-01-30 01:33:23
Hi Andreas,
----- Original Message -----
From: sleeper75se <sleeper75se_at_yahoo.se>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Tuesday, January 29, 2002 7:46 PM
Subject: [buildcheapeeg] Re: Is it time yet?
Answer part 1/2:
> > Then some SPICE simulations should be done to see if the
> > DRL circuit is stable under all possible conditions.
>
> Is the structure of the DRL finished though? I'd like to have a look
> at it :o)
Yes. Here it is. (in the attachment)
You can torture the DRL now in your SPICE simulation by testing the
performance under all possible conditions.
I have used some third party models (viewpoint of LinearTechnology ;-) )
like the TI INA114 and TLC272. You must copy the *.sub into the
"\SwCADIII\lib\sub" directory and all *.asy to "\SwCADIII\lib\sym\Opamps"
The stability of the original DRL design (from biosemi) looks very good
up to a user capacitance of 300pF and a DRL electrode resistance of 20k.
(see phase margin at 0 dB)
> > When all this is done, the resulting changes will be
> > inserted in the eagle schematic and a modified pcb layout
> > will be done. After that the first modularEEG prototype
> > can be built.
>
> Ok, good luck!
Thanks !
Regards,
Joerg
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