From: sleeper75se (sleeper75se_at_yahoo.se)
Date: 2002-03-06 02:34:21
--- In buildcheapeeg_at_yahoogroups.com, "Joerg Hansmann" <info_at_jhansmann.de> wrote:
> > * IC7 has no ground plane that prevents
> > capacitive coupling between the traces
> > under it and the chip substrate.
>
> The chip substate is IMO on V- or AGND. Why should capacitive
> coupling be a problem ?
This is again something I picked up somewhere. The chip die (and
bonding wires) forms a plate capacitor with the underlying copper.
The capacitance is so low so that only HF will pass into the chip,
meaning this particular consideration applies more to high-speed
digital and mixed-signal circuits, where it is vital. However, better
safe than sorry...?
>
> > Looks like Eagle has
> > messed up though.
>
> You really like EAGLE, do you ? :-P
Yeah, love it. Especially the 700k pdfs you get when you print the
schematic through Acrobat Distiller. :-p
...
> I have just uploaded the recent (hopefully final) 1.15 version
> (modEEGamp1_15_std_*.*) on
Looks ok! (Personally I think it's too big, but that has no bearing
on the quality. :-)
Just one more comment (I hope you find them helpful?) on
modEEGamp1_15_std_brd_both.png:
The gap between the trace leaving IC1-pin 7 and the bottom plane
looks awfully small compared to the rest. The same thing happens with
the upper-left trace going from the capacitor to the left of IC2. Any
unwanted copper bridges are easy to remove with a knife, but the
result is prettier if done before etching.
Good luck with the building!
Regards,
Andreas
This archive was generated by hypermail 2.1.4 : 2002-07-27 12:28:39 BST