From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2002-06-06 14:03:22
Hi Andreas,
----- Original Message -----
From: sleeper75se <sleeper75se_at_yahoo.se>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Saturday, May 25, 2002 2:42 AM
Subject: [buildcheapeeg] Cheap design uploaded
...
>
> Ok, anyone interested? Questions or comments?
I am referring to "Schematic.pdf" downloading date: 020604
1.) The ESD protection Q100..104 is located _before_ any HF blocking. So it will demodulate all HF especially AM signals
2) The input time constant of (C147 / 2 ) * R130 = 50 seconds is far too high for practical use:
After an big artifact you will have to wait about 3 times the timeconstant until the trace settles.
3) The DRL circuit with U101A is basically an integrator. That means to get a stable DC operation point
the output must be _DC_ coupled to the input stages. Otherwise U101A will simply integrate some offset voltages until it saturates.
So I am quite sure that your DRL will not work.
4) input noise voltage and current seems to be well designed and around 1uVp-p (0.1Hz .. 10Hz)
5) The calibration circuit with 4060B produces 2 frequencies 1024 Hz and 4096 Hz that
seem to be outside the frequency band of interest. Why that ?
6) What total offset voltage RTO (at output) do you expect, when closing JP100 for DC operation ?
Regards,
Joerg
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