From: Joerg Hansmann (info_at_jhansmann.de)
Date: 2002-06-07 10:16:51
Hi Andreas,
----- Original Message -----
From: sleeper75se <sleeper75se_at_yahoo.se>
To: <buildcheapeeg_at_yahoogroups.com>
Sent: Thursday, June 06, 2002 8:06 PM
Subject: [buildcheapeeg] Re: Cheap design uploaded
> Hi Joerg,
>
> this was not fun reading for me, but you have pointed out the weak
> spots, and I really appreciate it. Thanks.
>
> Could you please take some time considering these fixes (schematic
> not updated yet) and say what you think?
>
> 1) ESD protection / HF-blocking.
>
> The transistors will be placed between the inamp and the HF caps.
This placement should solve the assumed problem.
> 2) Settling time, and 3) DRL
>
> I really want the DRL to work, so I guess the input capacitors will
> have to go. :-(.
Not necessarily. You also have the option to redesign the DRL circuit
from an I-controller to a more appropriate type for this application
e.g. PD-controller.
You can easily do that in LTSpice in the bode-plot of the loop-gain
(to get a nice phase margin).
You only need to model the first stage and the DRL and the user/electrodes
(a simplified user-model with some Rs and Cs will certainly be enough).
> Of course, the settling time then drops to 3 seconds, which is nice.
The settling time problem could be solved with MOS transistors (or better:
analog switches) on each side of the coupling C that discharge both the
electrode polarization voltage and the coupling C when the gate-input goes high.
Controlling the swiches could be done from the uC (e.g. if for 2 seconds
the ADC-input is possibly out of range, for a certain time the analog switch
is turned on )
>
> 4) Input noise (1uVp-p)
>
> The INA126 is just $2.50, so one can't really complain. Is it too
> noisy you think? (Not sure if you are being ironic here...)
No. I think 1uVp-p is a quite reasonable and usable value.
> Remember
> that you get less noise when you look at narrower frequency bands.
>
> 5) 4060B oscillator/counter outputs
>
> Only 8, 32 and 512Hz are actually connected to something. I labeled
> all outputs as a reminder to myself.
I thought the numbers were the divisors. My fault.
However IMO a low frequency like 1Hz or 0.5Hz would be more important
than 512Hz because the higher frequencies are already present as a part
of the fourier-series (or was it Taylor ?).
> 6) Total RTO offset - JP100 jumper
>
> That is a remnant from previous designs (copy and paste), so I don't
> expect anyone to really use that unless they have better parts. Both
> the INA126 and TL064 have quite horrible offsets, so in total you get
> 1.85V worst case, ((250uV * 125 + 15mV) * 40) with the jumper closed.
Quite much.
> With the jumper open, it is 0.6V max originating in the second gain
> stage (TL064) (0.3V typ).
>
> Hmm, that is not too good either...
> Replacing the TL064 with an LP324 lowers the offset to max 0.16V
> (0.08V typ). (LP324 datasheet:
> http://www.elfa.se/pdf/73/730/07303241.pdf) Is it good enough?
This should be good enough. (BTW. because of the offset amplification,
I have used several AC-coupled stages with relatively low amplification
in the modularEEG. This allows the usage of cheap opamps and holds the
offset voltage (RTO) low)
> Once again, thanks.
That's all right!
> I hope you have time to comment on these
> suggestions.
Of course!
Regards,
Joerg
This archive was generated by hypermail 2.1.4 : 2002-07-27 12:28:43 BST